LTC1297DI datasheet(14/24 Pages) LINER

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LTC1292/LTC1297

APPLICATI

I FOR ATIO

Source Resistance

The analog inputs of the LTC1292/LTC1297 look like a

100pF capacitor (CIN) in series with a 500Ω resistor (RON)

(Figures 10a and 10b). CIN gets switched between (+) and

(–) inputs once during each conversion cycle. Large

external source resistors and capacitances will slow the

settling of the inputs. It is important that the overall RC

time constant is short enough to allow the analog inputs to

settle completely within the allowed time.

“+” Input Settling

The input capacitor for the LTC1292 is switched onto the

“+” input during the sample phase (tSMPL, see Figures 11a,

11b and 11c). The sample period can be as short as tWHCS

+ 1/2 CLK cycle or as long as tWHCS + 1 1/2 CLK cycles

before a conversion starts. This variability depends on

where CS falls relative to CLK. The voltage on the “+” input

must settle completely within the sample period. Minimizing

RSOURCE+ and C1 will improve the settling time. If large “+”

input source resistance must be used, the sample time can

be increased by using a slower CLK frequency. With the

minimum possible sample time of 3.0

µs, RSOURCE+ < 2.0k

and C1 < 20pF will provide adequate settling time.

The sample period for the LTC1297 starts on the falling

edge of CS and ends on the falling edge of the first CLK

Figure 11a. Setup Time (tsuCS) Is Met for the LTC1292

“+” and “–” Input Settling Windows

(Figure 12). The length of the sample period is tsuCS +0.5

CLK cycles. Again, the voltage on the “+” input must settle

completely within the sample period. If large “+” input

source resistance must be used, the sample time can be

increased by using a slower CLK frequency or by increasing

Figure 10a. Analog Input Equivalent Circuit for the LTC1292

Figure 10b. Analog Input Equivalent Circuit for the LTC1297

↑ R

500

Ω

tWHCS

+ 0.5 CLK

CIN

100pF

LTC1292

“+”

INPUT

RSOURCE +

VIN +

“–”

INPUT

RSOURCE –

VIN –

LTC1292/7 F10a

↓ R

500

Ω

tsuCS

+ 0.5 CLK

CIN

100pF

LTC1297

“+”

INPUT

RSOURCE +

VIN +

“–”

INPUT

RSOURCE –

VIN –

LTC1292/7 F10b

DOUT

CLK

B11

HI-Z

B10

LTC1292/7 F11a

1ST BIT TEST (–) INPUT MUST

SETTLE DURING THIS TIME

tSUCS

tWHCS

tSMPL

(+) INPUT MUST SETTLE DURING THIS TIME

(+) INPUT

(–) INPUT

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