LTC1297DI datasheet(16/24 Pages) LINER

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LTC1292/LTC1297

Figure 12. “+” and “–” Input Settling Windows for the LTC1297

“–” input voltage be free of noise and settle completely

during the first CLK cycle of the conversion. Minimizing

RSOURCE– and C2 will improve settling time. If large “–”

input source resistance must be used the time can be

extended by using a slower CLK frequency. At the maximum

CLK frequency of 1MHz, RSOURCE– < 250Ωand C2 < 20pF

will provide adequate settling.

Input Op Amps

When driving the analog inputs with an op amp it is

important that the op amp settles within the allowed time

(see Figures 11a, 11b, 11c and 12). Again the “+” and

“–” input sampling times can be extended as described

above to accommodate slower op amps. Most op amps

including the LT1006 and LT1013 single supply op amps

can be made to settle well even with the minimum settling

windows of 3.0

µs for the LTC1292 or 6.0µs for the

LTC1297 (“+” input) and 1

µs (“–” input) that occurs at the

maximum clock rate of 1MHz. Figures 13 and 14 show

examples of both adequate and poor op amp settling.

HORIZONTAL: 500ns/DIV

HORIZONTAL: 20

µs/DIV

Figure 13. Adequate Settling of Op Amp Driving Analog Input

Figure 14. Poor Op Amp Settling Can Cause A/D Errors

APPLICATI

I FOR ATIO

DOUT

CLK

B11

HI-Z

B10

LTC1292/7 F12

1ST BIT TEST (–) INPUT MUST

SETTLE DURING THIS TIME

tWHCS

tSMPL

(+) INPUT MUST SETTLE

DURING THIS TIME

(+) INPUT

(–) INPUT

tsuCS

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