LTC1297DI datasheet(18/24 Pages) LINER

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LTC1292/LTC1297

APPLICATI

I FOR ATIO

Figures 17 and 18 show examples of both adequate and

poor settling. Using a slower CLK will allow more time

for the reference to settle. Even at the maximum CLK

rate of 1MHz most references and op amps can be

made to settle within the 1

µs bit time. For example the

LT1027 will settle adequately. With a 10

µF bypass

capacitor at VREF the LT1021 can also be used.

Reduced Reference Operation

The effective resolution of the LTC1292/LTC1297 can

be increased by reducing the input span of the con-

verter. The LTC1292/LTC1297 exhibit good linearity

over a range of reference voltages (see typical perfor-

mance characteristics curves of Change in Linearity vs

Reference Voltage). Care must be taken when operat-

ing at low values of VREF because of the reduced LSB

step size and the resulting higher accuracy requirement

placed on the converter. Offset and noise are factors

that must be considered when operating at low VREF

values. The internal reference for VREF has been tied to

the GND pin. Any voltage drop from the GND pin to the

ground plane will cause a gain error.

Offset with Reduced VREF

The offset of the LTC1292/LTC1297 has a larger effect

on the output code when the A/D is operated with a

reduced reference voltage. The offset (which is typi-

cally a fixed voltage) becomes a larger fraction of an

LSB as the size of the LSB is reduced. The typical

performance characteristics curve of Unadjusted Off-

set Error vs Reference Voltage shows how offset in

LSBs is related to reference voltage for a typical value

of VOS. For example a VOS of 0.1mV, which is 0.1LSB

with a 5V reference becomes 0.4LSB with a 1.25V

reference. If this offset is unacceptable, it can be

corrected digitally by the receiving system or by offset-

ting the –IN input to the LTC1292/LTC1297.

Noise with Reduced VREF

The total input referred noise of the LTC1292/LTC1297

can be reduced to approximately 200

µVP-P using a

ground plane, good bypassing, good layout techniques

and minimizing noise on the reference inputs. This

noise is insignificant with a 5V reference input but will

version technique (see Figure 16). During each bit test

of the conversion (every CLK cycle) a capacitive current

spike will be generated on the reference pin by the A/D.

These current spikes settle quickly and do not cause a

problem. If slow settling circuitry is used to drive the

reference input, take care to insure that transients

caused by these current spikes settle completely during

each bit test of the conversion.

RON

8pF TO 40pF

LTC1292

LTC1297

REF+

ROUT

VREF

EVERY

CLK CYCLE

REF –

LTC1292/7 F16

Figure 16. Reference Input Equivalent Circuit

HORIZONTAL: 1

µs/DIV

Figure 17. Adequate Reference Settling (LT1027)

HORIZONTAL: 10

µs/DIV

Figure 18. Poor Reference Settling Can Cause A/D Errors

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