6

LTC1292/LTC1297

CC

HARA TERISTICS

A

TYPICALPERFOR

CE

100

0.2

0.4

0.6

0.8

1.0

1k

10k

100k

LTC1292/7G13

0

CLK = 1MHz

+

–

+IN

–IN

Maximum Filter Resistor vs

Cycle Time

PI FU CTIO S

#

PIN

FUNCTION

DESCRIPTION

1

CS

Chip Select Input

A logic low on this input enables the LTC1292/LTC1297. Power shutdown is activated on the LTC1297 when

CS is brought high.

2, 3

+IN, –IN

Analog Inputs

These inputs must be free of noise with respect to GND.

4

GND

Analog Ground

GND should be tied directly to an analog ground plane.

Reference Input

The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND.

Digital Data Output

The A/D conversion result is shifted out of this output.

7

CLK

Shift Clock

This clock synchronizes the serial data transfer.

Positive Supply

This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.

* MAXIMUM CLK FREQUENCY REPRESENTS THE

CLK FREQUENCY AT WHICH A 0.1LSB SHIFT IN

THE ERROR AT ANY CODE TRANSITION FROM ITS

1MHz VALUE IS FIRST DETECTED.

RESISTOR VALUE AT WHICH A 0.1LSB CHANGE IN

FULL SCALE ERROR FROM ITS VALUE AT

CYCLE TIME (µs)

10

100

1k

10k

10

1k

10k

LTC1292/7 G14

1

100

+

–

Maximum Clock Rate vs

Source Resistance

100

1

10

100

1000

10000

LTC1292/7 G15

+

–

0V TO 5V INPUT STEP

Sample-and-Hold Acquisition

Time vs Source Resistance

Input Channel Leakage Current vs

Temperature

AMBIENT TEMPERATURE (°C)

–50

0

100

300

400

500

1000

700

–10

30

50

130

LTC1292/7 G16

200

800

900

600

–30

10

70

90 110

ON CHANNEL

OFF CHANNEL

GUARANTEED

Noise Error vs Reference Voltage

REFERENCE VOLTAGE (V)

0

0

0.25

0.75

1.00

1.25

2

4

5

2.25

0.50

13

1.50

1.75

2.00

LTC1292/7 G17

LTC1292/LTC1297