LTC1297DI datasheet(15/24 Pages) LINER

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LTC1292/LTC1297

APPLICATI

I FOR ATIO

Figure 11b. Setup Time (tsuCS) Is Met for the LTC1292

Figure 11c. Setup Time (tsuCS) Is Not Met for the LTC1292

tsuCS. With the minimum possible sample time of 6µs,

RSOURCE+ < 5k and C1 < 20pF will provide adequate

settling time. In general for both the LTC1292 and LTC1297

keep the product of the total resistance and the total

capacitance less than tSMPL/9. If this condition can not be

met, then make C1 > 0.47

µF (see RC Input Filtering

section).

“–” Input Settling

At the end of the sample phase the input capacitor switches

to the “–” input and the conversion starts (see Figures 11a,

11b, 11c and 12). During the conversion, the “+” input

voltage is effectively “held” by the sample-and-hold and

will not affect the conversion result. It is critical that the

DOUT

CLK

B11

HI-Z

B10

LTC1292/7 F11b

1ST BIT TEST (–) INPUT MUST

SETTLE DURING THIS TIME

tWHCS

tSMPL

(+) INPUT MUST SETTLE DURING THIS TIME

(+) INPUT

(–) INPUT

DOUT

CLK

B11

HI-Z

B10

LTC1292/7 F11c

1ST BIT TEST (–) INPUT MUST

SETTLE DURING THIS TIME

tWHCS

tSMPL

(+) INPUT MUST SETTLE DURING THIS TIME

(+) INPUT

(–) INPUT

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