LTC1417IGN datasheet(9/32 Pages) LINER

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LTC1417

CONVERSION DETAILS

The LTC1417 uses a successive approximation algorithm

and an internal sample-and-hold circuit to convert an

analog signal to a 14-bit serial output. The ADC is com-

plete with a precision reference and an internal clock. The

control logic provides easy interface to microprocessors

and DSPs (please refer to Digital Interface section for the

data format).

Conversion start is controlled by the CONVST input. At the

start of the conversion, the successive approximation

begun, it cannot be restarted.

During the conversion, the internal differential 14-bit

capacitive DAC output is sequenced by the SAR from the

most significant bit (MSB) to the least significant bit (LSB).

Referring to Figure 1, the AIN+ and AIN– inputs are con-

nected to the sample-and-hold capacitors (CSAMPLE) dur-

ing the acquire phase and the comparator offset is nulled by

the zeroing switches. In this acquire phase, a minimum

delay of 500ns will provide enough time for the sample-

and-hold capacitors to acquire the analog signal. During

the convert phase, the comparator zeroing switches open,

placing the comparator in compare mode. The input

switches connect the CSAMPLE capacitors to ground,

transferring the differential analog input charge onto the

summing junction. This input charge is successively

compared with the binary weighted charges supplied by

the differential capacitive DAC. Bit decisions are made by

the high speed comparator. At the end of a conversion, the

differential DAC output balances the AIN+ and AIN– input

charges. The SAR contents (a 14-bit data word) that

represent the difference of AIN+ and AIN– are output

through the serial pin DOUT.

DC Performance

One way of measuring the transition noise associated with

a high resolution ADC is to use a technique where a DC

signal is applied to the input of the ADC and the resulting

output codes are collected over a large number of conver-

sions. For example in Figure 2, the distribution of output

code is shown for a DC input that has been digitized 4096

times. The distribution is Gaussian and the RMS code

transition is about 0.33LSB.

Figure 1. Simplified Block Diagram

1417 F01

SHIFT

SAR

CDAC

–

VDAC

–

VDAC

–

COMP

DOUT

HOLD

AIN

–

ZEROING SWITCHES

CSAMPLE

–

CSAMPLE

HOLD

SAMPLE

APPLICATIONS INFORMATION

CODE

–2

1500

2000

2500

1417 F02

1000

500

–1

3000

3500

4000

Figure 2. Histogram for 4096 Conversions

DYNAMIC PERFORMANCE

The LTC1417 has excellent high speed sampling capabil-

ity. FFT (Fast Fourier Transform) test techniques are used

to test the ADC’s frequency response, distortion and

noise performance at the rated throughput. By applying

a low distortion sine wave and analyzing the digital output

using an FFT algorithm, the ADC’s spectral content can be

examined for frequencies beyond the fundamental.

Figure 3 shows a typical LTC1417 FFT plot.

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