LTC1417IGN datasheet(14/32 Pages) LINER

14 / 32 page

LTC1417

APPLICATIONS INFORMATION

Figure 11b. Offset and Full-Scale Adjust Circuit

If – 5V Is Available

Figure 11a. Offset and Full-Scale Adjust Circuit

If – 5V Is Not Available

50k

ANALOG INPUT

1417 F11a

100

Ω

24k

48k

24k

50k

47k

0.1

µF

100

Ω

LTC1417

AIN

–

VREF

REFCOMP

AGND V

VDD

OFFSET

ADJ

ANALOG INPUT

1417 F11b

–5V

100

Ω

50k

ADJ

OFFSET

ADJ

24k

50k

47k

0.1

µF

LTC1417

AIN

–

VREF

REFCOMP

AGND V

VDD

Unipolar Offset and Full-Scale Error Adjustment

In applications where absolute accuracy is important,

offset and full-scale errors can be adjusted to zero. Offset

error must be adjusted before full-scale error. Figures

11a and 11b show the extra components required for full-

scale error adjustment. Zero offset is achieved by adjust-

ing the offset applied to the AIN– input. For zero offset

error, apply 125

µV (i.e., 0.5LSB) at the input and adjust

the offset at the AIN– input until the output code flickers

between 0000 0000 0000 00 and 0000 0000 0000 01. For

full-scale adjustment, an input voltage of 4.095625V

(FS – 1.5LSBs) is applied to AIN+ and R2 is adjusted until

the output code flickers between 1111 1111 1111 10 and

1111 1111 1111 11.

Bipolar Offset and Full-Scale Error Adjustment

Bipolar offset and full-scale errors are adjusted in a

similar fashion to the unipolar case using the circuit in

Figure 11b. Again, bipolar offset error must be adjusted

before full-scale error. Bipolar offset error adjustment is

achieved by adjusting the offset applied to the AIN– input.

For zero offset error, apply – 125

µV (i.e., –0.5LSB) at AIN+

and adjust the offset at the AIN– input until the output code

flickers between 0000 0000 0000 00 and 1111 1111 1111

11. For full-scale adjustment, an input voltage of 2.047625V

(FS – 1.5LSBs) is applied to AIN+ and R2 is adjusted until

the output code flickers between 0111 1111 1111 10 and

0111 1111 1111 11.

BOARD LAYOUT AND GROUNDING

To obtain the best performance from the LTC1417, a

printed circuit board with ground plane is required. The

ground plane under the ADC area should be as free of

breaks and holes as possible, such that a low impedance

path between all ADC grounds and all ADC decoupling

capacitors is provided. It is critical to prevent digital noise

from being coupled to the analog input, reference or

analog power supply lines. Layout should ensure that

digital and analog signal lines are separated as much as

possible. In particular, care should be taken not to run any

digital track alongside an analog signal track.

An analog ground plane separate from the logic system

ground should be established under and around the ADC.

Pin 5 (AGND) and Pin 10 (DGND) and all other analog

grounds should be connected to this single analog ground

plane. The REFCOMP bypass capacitor and the VDD by-

pass capacitor should also be connected to this analog

ground plane. No other digital grounds should be con-

nected to this analog ground plane. Low impedance ana-

log and digital power supply common returns are essential

to low noise operation of the ADC and the foil width for

these tracks should be as wide as possible. In applications

where the ADC data outputs and control signals are

connected to a continuously active microprocessor bus, it

is possible to get errors in the conversion results. These

errors are due to feedthrough from the microprocessor to

the successive approximation comparator. The problem

can be eliminated by forcing the microprocessor into a

LTC1417IGN Datasheet(PDF) 14 Page - Linear Technology

LTC1417IGN Datasheet(HTML) 14 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL