LTC1417IGN datasheet(22/32 Pages) LINER

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LTC1417

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CONVST

EXTCLKIN

t10

tdEXTCLKIN

HOLD

SAMPLE

BUSY

SCLK

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12 11 10 987654321

FILL

ZEROS

D13

Hi-Z

DATA N

Hi-Z

(SAMPLE N)

DOUT

tCONV

1417 F20

D11

D12

CAPTURE ON

RISING CLOCK

D13

t12

t11

SCLK

VIL

VOH

VOL

DOUT

CAPTURE ON

FALLING CLOCK

tLSCLK

tHSCLK

LTC1417

BUSY

CONVST

EXTCLKIN

SCLK

DOUT

µP OR DSP

CLKOUT

INT

SCK

MISO

APPLICATIONS INFORMATION

Figure 20. External Conversion Clock Selected. Data Transferred After Conversion

Using an External SCLK. BUSY

↑ Indicates End of Conversion

Using an External Conversion Clock and an External

Data Clock. In Figure 20, data is also output after each

conversion is completed and before the next conversion is

started. An external clock is used for the conversion clock

and either another or the same external clock is used for

the SCLK. This mode is identical to Figure 19 except that

an external clock is used for the conversion. This mode

allows the user to synchronize the A/D conversion to an

external clock either to have precise control of the internal

bit test timing or to provide a precise conversion time. As in

Figure 19, this mode works when the SCLK frequency is

very low (less than 30kHz). However, the external conver-

sion clock must be between 30kHz and 9MHz to maintain

accuracy. If more than 16 SCLKs are provided, more zeros

will be filled in after the data word indefinitely. To select the

external conversion clock, apply an external conversion

clock to EXTCLKIN. The external SCLK is applied to SCLK.

RD can be used to gate the external SCLK such that data will

be clocked out only after RD goes low.

LTC1417IGN Datasheet(PDF) 22 Page - Linear Technology

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