LTC1417IGN datasheet(17/32 Pages) LINER

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LTC1417

DIGITAL INTERFACE

The LTC1417 operates in serial mode. The RD control input

is common to all peripheral memory interfacing. Only four

digital interface lines are required, SCLK, CONVST,

EXTCLKIN and DOUT. SCLK, the serial data shift clock can

be an external input or supplied by the LTC1417’s internal

clock.

Internal Clock

The ADC has an internal clock. Either the internal clock or

an external clock may be used as the conversion clock (see

Figure 15). The internal clock is factory trimmed to achieve

a typical conversion time of 1.8

µs, and a maximum con-

version time over the full operating temperature range of

2.5

µs. No external adjustments are required, and with the

guaranteed maximum acquisition time of 0.5

µs, through-

put performance of 400ksps is assured.

Conversion Control

Conversion start is controlled by the signal applied to the

CONVST input. A falling edge on the signal applied to the

CONVST pin starts a conversion. Once initiated, it cannot

be restarted until the conversion is complete. Converter

status is indicated by the BUSY output. BUSY is low during

a conversion.

Data Output

Output will be active when RD is low. A high RD will three-

state the ouput. In unipolar mode (VSS = 0V), the data will

be in straight binary format (corresponding to the unipolar

input range). In bipolar mode (VSS = –5V), the data will be

in two’s complement format (corresponding to the bipolar

input range).

Serial Output Mode

Conversions are started by a falling CONVST edge. After a

conversion is completed and the output shift register has

been updated, BUSY will go high and valid data will be

available on DOUT (Pin 9). This data can be clocked out

either before the next conversion starts or it can be clocked

out during the next conversion. To enable the serial data

output buffer and shift clock, RD must be low.

Figure 15 shows a function block diagram of the LTC1417.

There are two pieces to this circuitry: the conversion clock

selection circuit (EXTCLKIN and CLKOUT) and the serial

port (SCLK, DOUT and RD).

APPLICATIONS INFORMATION

THREE

STATE

BUFFER

THREE

STATE

BUFFER

• • •

SCLK

EXTCLKIN

BUSY

1417 F15

DOUT

CLKOUT

SHIFT

INTERNAL

CLOCK

DETECTOR

16 CONVERSION CLOCK CYCLES

EOC

DATA

OUT

CLOCK

INPUT

• • •

SAR

Figure 15. Functional Block Diagram

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