LTC1877 datasheet(11/16 Pages) LINER

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LTC1877

frequency is less than 550kHz, current is sunk continu-

ously, pulling down the PLL LPF pin. If the external and

internal frequencies are the same but exhibit a phase

difference, the current sources turn on for an amount of

time corresponding to the phase difference. Thus the

voltage on the PLL LPF pin is adjusted until the phase and

frequency of the external and internal oscillators are

identical. At this stable operating point the phase com-

parator output is high impedance and the filter capacitor

CLP holds the voltage.

The loop filter components CLP and RLP smooth out the

current pulses from the phase detector and provide a

stable input to the voltage controlled oscillator. The filter

component’s CLP and RLP determine how fast the loop

acquires lock. Typically RLP = 10k and CLP is 2200pF to

0.01

µF. When not synchronized to an external clock, the

internal connection to the VCO is disconnected. This

disallows setting the internal oscillator frequency by a DC

voltage on the VPLL LPF pin.

Efficiency Considerations

The efficiency of a switching regulator is equal to the

output power divided by the input power times 100%. It is

often useful to analyze individual losses to determine what

is limiting the efficiency and which change would produce

the most improvement. Efficiency can be expressed as:

Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage

of input power.

Although all dissipative elements in the circuit produce

losses, two main sources usually account for most of the

losses in LTC1877 circuits: VIN quiescent current and I2R

losses. The VIN quiescent current loss dominates the

efficiency loss at very low load currents whereas the I2R

loss dominates the efficiency loss at medium to high load

currents. In a typical efficiency plot, the efficiency curve at

very low load currents can be misleading since the actual

power lost is of no consequence as illustrated in Figure 6.

1. The VIN quiescent current is due to two components:

the DC bias current as given in the electrical character-

istics and the internal main switch and synchronous

switch gate charge currents. The gate charge current

APPLICATIONS INFORMATION

results from switching the gate capacitance of the

internal power MOSFET switches. Each time the gate is

switched from high to low to high again, a packet of

charge dQ moves from VIN to ground. The resulting

dQ/dt is the current out of VINthat is typically larger than

the DC bias current. In continuous mode, IGATECHG =

f(QT + QB) where QT and QB are the gate charges of the

internal top and bottom switches. Both the DC bias and

gate charge losses are proportional to VIN and thus

their effects will be more pronounced at higher supply

voltages.

2. I2R losses are calculated from the resistances of the

internal switches, RSW, and external inductor RL. In

continuous mode the average output current flowing

through inductor L is “chopped” between the main

switch and the synchronous switch. Thus, the series

resistance looking into the SW pin is a function of both

top and bottom MOSFET RDS(ON) and the duty cycle

(DC) as follows:

RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)

The RDS(ON) for both the top and bottom MOSFETs can

be obtained from the Typical Performance Charateristics

curves. Thus, to obtain I2R losses, simply add RSW to

RL and multiply the result by the square of the average

output current.

Other losses including CIN and COUT ESR dissipative

losses and inductor core losses generally account for less

than 2% total additional loss.

Figure 6. Power Lost vs Load Current

LOAD CURRENT (mA)

0.1

0.00001

0.001

100

1000

1877 F06

0.0001

0.01

0.1

VOUT = 1.5V

VOUT = 2.5V

VOUT = 3.3V

VIN = 4.2V

L = 10

µH

Burst Mode OPERATION

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