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LTC3609 Datasheet(PDF) 18 Page - Linear Technology

Part # LTC3609
Description  32V, 6A Monolithic Synchronous Step-Down DC/DC Converter
PDF  26 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC3609 Datasheet(HTML) 18 Page - Linear Technology

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LTC3609

3609fb
applicaTions inForMaTion
Figure6.DesignExample:5Vto32VInputto2.5V/6Aat550kHz
VOUT
2.5V AT
6A
GND
VIN
VIN
5V TO 32V
COUT1
100µF
x2
L1
1.2µH
CIN
4.7µF
50V
x2
+
LTC3609
SGND
26
NC
25
NC
24
VFB
23
ION
22
NC
21
SGND
20
FCB
19
ITH
18
VRNG
17
PGOOD
16
SGND
15
SGND
GND
VOUT
1
2
3
4
5
6
7
SW
SW
SW
8
9 10 11
12 13 14
40 39 38 37 36 35 34 33
INTVCC
INTVCC
32
PGOOD
31
VIN
30 29 28 27
SW
41
SW
42
SW
43
SW
44
SW
45
SW
46
SW
47
PVIN
48
PVIN
49
PVIN
50
PVIN
51
PVIN
52
3609 F06
CF
0.1µF
50V
RF1
1
CVCC
4.7µF
6.3V
EXTVCC
C4
0.01µF
INTVCC
INTVCC
JP1
CB1
0.22µF
DB
CMDSH-3
CSS
0.1µF
VIN
CVON
0.1µF
R1
9.53k
1%
RPG1
100k
RON
187k
1%
R2
30.1k
1%
R5
15.8k
CC1
1000pF
CC2
100pF
VOUT
CIN: MURATA GRM32ER71H475K
COUT: MURATA GRM435R60J107M
LI: CDEP851R2MC-50
KEEP POWER GROUND AND SIGNAL
GROUND SEPARATE. CONNECT AT
ONE POINT.
2
DesignExample
As a design example, take a supply with the following
specifications: VIN = 5V to 32V (12V nominal), VOUT =
2.5V ±5%, IOUT(MAX) = 6A, f = 550kHz. First, calculate the
timing resistor with VON = VOUT:
R
V
V
kHz
pF
k
ON =
(
)(
)(
)
=
2 5
2 4
550
10
187
.
.
and choose the inductor for about 40% ripple current at
the maximum VIN:
L =
2.5V
550kHz
(
) 0.4
( ) 6A
( )
1− 2.5V
32V
=1.8µH
Selecting a standard value of 1.5µH results in a maximum
ripple current of:
Δ
IL =
2.5V
550kHz
(
) 1.5µH
(
)
1– 2.5V
12V
= 2.4A
Next, set up VRNG voltage and check the ILIMIT. Tying VRNG
to GND will set the typical current limit to 9A, and tying
VRNG to 1.2V will result in a typical current around 14A.
CIN is chosen for an RMS current rating of about 5A at
85°C. The ceramic output capacitors are chosen for an
ESR of 0.002Ω to minimize output voltage changes due
to inductor ripple current and load steps. The ripple volt-
age is:
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR)
= (2.4A) (0.002Ω) = 4.8mV
and a 0A to 6A load step will only cause an output
change of:
∆VOUT(STEP) = ∆ILOAD (ESR) = (6A) (0.002Ω) = 12mV
An optional 22µF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 6.



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