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LTC5585 Datasheet(PDF) 28 Page - Linear Technology

Part # LTC5585
Description  Wideband IQ Demodulator with IIP2 and DC Offset Control
PDF  38 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC5585 Datasheet(HTML) 28 Page - Linear Technology

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LTC5585
28
5585fb
For more information www.linear.com/LTC5585
IM2 Suppression Example
IM2 adjustment circuitry can be used in a typical trans-
ceiver loop-back application as shown in Figure 27. In
this example a 2-tone SSB training source of f1 = 20MHz
and f2 = 21MHz is generated in DSP and upconverted
by the LTC5588-1 quadrature modulator to RF tones at
1970MHz and 1971MHz using an LO source at 1950MHz.
A narrowband RF filter is required to remove the IM2
component generated by the LTC5588-1. During the
loopback test these RF tones are routed through high
isolation switches and an attenuation pad to the LTC5585
demodulator input. The tones are then downconverted by
the same LO source at 1950MHz to produce two tones
at the baseband outputs of 20MHz and 21MHz plus an
IM2 impairment signal at 1MHz. After baseband chan-
nel filtering and amplification the output of the ADC is
filtered by a 1MHz bandpass filter in DSP to isolate the
IM2 tone. The power in this tone is calculated in DSP and
then a 1-D minimization algorithm is applied to calculate
the correction signal for the IP2I control voltage pin. The
1-D minimization algorithm can be implemented in many
ways such as golden-section search, backtracking or
Newton’s method.
Enable Interface
A simplified schematic of the EN pin is shown in Figure 28.
TheenablevoltagenecessarytoturnontheLTC5585is2V.
To disable or turn off the chip, this voltage should be below
0.3V. If the EN pin is not connected, the chip is disabled.
APPLICATIONS INFORMATION
Figure 27. Block Diagram for a Direct Conversion Transceiver with IM2 Adjustment. Only the I-Channel Is Shown
Figure 28. Simplified Schematic of the EN Pin Interface
Figure 29. Simplified Schematic of the EDC Pin Interface
RMS
DETECTION
1MHz BPF
DSP
DAC
ADC
IP2I
fLO = 1950MHz
f1 = 20MHz
f2 = 21MHz
5585 F27
LNA
LTC5585
LOOPBACK
LTC5588-1
1-D
MINIMIZATION
ALGORITHM
DAC
PA
+
100k
EN
LTC5585
GND
5585 F28
VCC
100k
EN
100k
100k
EDC
LTC5585
5585 F29
VCC
GND
Figures 29 and 30 show the simplified schematics for the
EDC and EIP2 pins



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