RT7310 datasheet(4/12 Pages) RICHTEK

4 / 12 page

RT7310

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

DS7310-00

October

2014

Primary-Side Constant-Current Regulation

RT7310 needs no shunt regulator and opto-coupler at

the secondary side to achieve the output current

regulation. Figure 3 shows several key waveforms of a

conventional flyback converter in Quasi-Resonant (QR)

mode, in which VAUX is the voltage on the auxiliary

winding of the transformer.

VAUX

VIN

IQ1

(VGS)

(VOUT + Vf) x NA / NS

VIN x NA / NP

IDOUT

Clamped by

controller

VDS

Figure 3. Key Waveforms of a Flyback Converter

Voltage Clamping Circuit

RT7310 provides a voltage clamping circuit at ZCD pin

since the voltage on the auxiliary winding is negative

when the main switch is turned on. The lowest voltage

on ZCD pin is clamped near zero to prevent the IC from

being damaged by the negative voltage. Meanwhile,

the sourcing ZCD current (IZCD_SH), flowing through the

upper resistor (RZCD1), is sampled and held to be a

line-voltage-related

signal

for

propagation

delay

compensation. RT7310 embeds the programmable

propagation delay compensation through CS pin. A

sourcing current ICS (equal to IZCD_SH x KPC) applies a

voltage offset (ICS x RPC) which is proportional to line

voltage on CS to compensate the propagation delay

effect. Thus, the total power limit or output current can

be equal at high and low line voltage.

Quasi-Resonant Operation

For improving converter

’s efficiency, RT7310 detects

valleys of the Drain-to-Source voltage (VDS) of main

switch and turns it on near the selected valley. For the

valley detections, a pulse of the

“valley signal” is

generated after a 500ns (typ.) delay time which starts at

which the voltage (VZCD) on ZCD pin goes down and

reaches the voltage threshold (VZCDT, 0.4V typ.).

During the rising of the VZCD, the VZCD must reach the

voltage threshold (VZCDA, 0.5V typ.). Otherwise, no

pulse of the

“valley signal” is generated. Moreover, if

the timing when the falling VZCD reaches VZCDT is not

later than a mask time (tMASK, 2s typ.) then the valley

signal will be masked and regards as no valley, as

shown in Figure 4.

VZCD

Valley

Signal

PWM

500ns

tMASK

VZCDA

VZCDT

Figure 4. Valley Signal Generating Method

Figure 5 illustrates how valley signal triggers PWM. If

no valley signal detected for a long time, the next PWM

is triggered by a starter circuit at end of the interval

(tSTART, 75s typ.) which starts at the rising edge of the

previous PWM signal. A blanking time (tS(MIN), 8.5s

typ.), which starts at the rising edge of the previous

PWM signal, limits minimum switching period. When

the tS(MIN) interval is on-going, all of valley signals are

not allowed to trigger the next PWM signal. After the

end of the tS(MIN) interval, the coming valley will trigger

the next PWM signal. If one or more valley signals are

detected during the tS(MIN) interval and no valley is

detected after the end of the tS(MIN) interval, the next

PWM signal will be triggered automatically at end of the

tS(MIN) + 5s (typ.).

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