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RT9832 Datasheet(PDF) 10 Page - Richtek Technology Corporation

Part # RT9832
Description  PWM Duty Generator with Adjustable Duty Setting
PDF  12 Pages
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Manufacturer  RICHTEK [Richtek Technology Corporation]
Direct Link  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT9832 Datasheet(HTML) 10 Page - Richtek Technology Corporation

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RT9832
10
DS9832-00
January 2013
www.richtek.com
©
Copyright
2013 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
Application Information
The RT9832 is a PWM duty generator with adjustable
duty setting. The PWM frequency is fixed 0.5Hz typically.
The device operates over a wide input voltage range from
2.8V to 20V.
Capacitor Selection
Input ceramic capacitor of 0.47
μF is recommended for the
RT9832. For better voltage filtering, ceramic capacitors
with low ESR are recommended. X5R and X7R types are
suitable because of their wider voltage and temperature
ranges.
UVLO/OTP
As the input voltage is lower than a specified value, the
chip will enter protection mode to prevent abnormal
function. As the die temperature is higher then 160
°C, the
chip will also enter protection mode. The output will be
turned off during protection mode to prevent abnormal
operation.
Duty Cycle Setting
The duty cycle is set by an external resistor on RSET
pin, and the PWM duty is adjustable from 1% to 100%,
according to following equation :
Figure 2. Derating Curve of Maximum Power Dissipation
0.0
0.2
0.4
0.6
0.8
1.0
025
50
75
100
125
Ambient Temperature (°C)
Four-Layer PCB
SET
R
Duty Cycle =
10k
Ω
When the RSET is floating, the duty cycle is set at 50%
typically.
Enable
The RT9832 enable is an active low logic signal control for
output. The enable pin is pulled to low with internal
resistors. When enable logic is low, a PWM duty will be
on; when enable logic is high, a PWM duty will be off.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX)
− TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and
θJAis the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125
°C. The junction to
ambient thermal resistance,
θJA, is layout dependent. For
WL-CSP-6B 0.8x1.2 (BSC) package, the thermal
resistance,
θJA, is 148°C/W on a standard JEDEC 51-7
four-layer thermal test board. The maximum power
dissipation at TA = 25
°C can be calculated by the following
formula :
PD(MAX) = (125
°C − 25°C) / (148°C/W) = 0.68W for
WL-CSP-6B 0.8x1.2 (BSC) package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance,
θJA. The derating curve in Figure 2 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.



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