2.125Gbps, 3.3V

Quad-Port Bypass with Repeater

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7

Detailed Description

The MAX3752 quad PBC consists of an input buffer, a

clock/data recovery circuit (for optional data recovery),

four serially connected port bypass circuits, and an

output buffer (Figure 1). The circuit design is optimized

for both high-speed (2Gbps) and low-voltage (+3.3V)

operation.

Input Buffer

The input buffer provides line termination and level con-

version. It accepts a differential input voltage of 200mV

to 2200mV at the IN+ and IN- pins. Internal resistors

terminate each input to 75

Ω (150Ω total between the

two inputs), eliminating the need for external termina-

tion resistors in most applications (see Applications

Information for a suggested interface to 50

Ω systems).

Clock and Data Recovery

The purpose of the clock and data recovery (CDR) is to

improve jitter transfer performance by attenuating jitter

that may be present in the input data. The CDR can

recover data signals that are corrupted by up to 0.7UI

ery is not needed, the CDR may be disabled in order to

save power.

The input buffer drives the CDR circuit, as well as one

input of a 2:1 multiplexer. A TTL high on the CDR enable

pin (CDREN) enables the CDR and connects the CDR

data output to the port bypass circuits. The recovered

clock signal is available for test purposes at LOUT1 (the

output of the first port bypass circuit) when the clock

enable input (CLKEN) is set to a TTL high level. A TTL

low on CDREN disables the CDR and connects the

input buffer output directly to the port bypass circuits.

Port Bypass Circuits

The output of the 2:1 input multiplexer drives a cascad-

ed series of four PBCs. Each PBC consists of a differen-

tial output buffer, a differential input buffer, and a 2:1

multiplexer. The multiplexer select input (SELn) controls

which multiplexer input is connected to the multiplexer

output. A TTL low on the multiplexer select pin causes

the data signal from the previous stage to be connected

to the multiplexer output (port bypass mode). A TTL

high on the multiplexer select pin causes the data signal

from the input buffer to be connected to the multiplexer

output (port enable mode). The output of the last PBC

drives the output buffer.

Output Buffer

The output signal of the last PBC drives the differential

high-power output buffer. The output buffer drives the

output port (OUT±). Internal resistors terminate each

output to 75

Ω (150Ω total between the two outputs),

eliminating the need for external termination resistors in

most applications (see Applications Information for a

suggested interface to 50

Ω systems). The output buffer

produces a differential output voltage of 1000mV to

1600mV when driving a differential 150

Ω load.

D0 Q

D1

MAX3752

TTLIN

SEL4

D0 Q

D1

TTLIN

SEL3

D0 Q

D1

TTLIN

SEL2

D0 Q

D1

TTLIN

SEL1

IN+

IN-

GND

OUT+

OUT-

D1

Q

D0

D0 Q

D1

TTLIN

CDREN

CLKEN

TTLIN

CF

CFM

CFP

CLK

CDR

EN

LOCK

LOCKEN

DOUT

DIN

Figure 1. Functional Diagram