 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
IRMCF171 Datasheet(PDF) 10 Page - International Rectifier |
|
|
|||||||||||||||||||||||||||||
IRMCF171 Datasheet(HTML) 10 Page - International Rectifier |
|
|
10 / 36 page  IRMCF171 10 www.irf.com © 2013 International Rectifier April 20, 2013 P1.2/TXD P1.1/RXD P1.3/SYNC/SCK XTAL0 PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL GATEKILL AIN0 – AIN4 Host Microcontroller (RS232C) Digital I/O Control System Clock 4MHz Crystal Analog Output XTAL1 P1.4/CAP P3.0/CS1 RESET P5.1/TDI JTAG Control (Flash programming & Emulation) TCK P5.2/TMS TDO IFBC+ IFBC- IFBCO Analog inputs (0-1.2V) AVDD 1.8V AVSS VDD1 3.3V VSS CMEXT AIN5+ AIN 5- AIN5O Optional External Voltage Reference (0.6V) P2.7/AOPWM1 SCL/SO-SI SDA/CS0 Other Communication (I2C) Frequency Synthesizer RS232 C I2C/SPI PORT1 PORT2 RESET PWM1 JTAG Interface Low Loss Space Vector PWM S/H S/H 8051 CPU Dual Port Memory (2 KB) & MCE Memory (12 KB) Motion Control Modules Motion Control Sequencer 12bit A/D & MUX System clock Local RAM (2 KB) Program FLASH (64 KB) System Reset Watchdog Timer Timers IRMCF171 AREF PORT3 P1.0/T2 P1.5 P2.0/NMI P3.2/INT0 5 3.3V 1.8V Voltage Regulator VDDCAP 3.3V P3.3/INT1 Motor HVIC Gate Drive IRS2336 D Single Shunt Current Sensing P3.1/AOPWM2 Buffered Analog Input PWM2 Figure 5. IRMCF171 Single Shunt Connection Diagram 4.1 8051 Peripheral Interface Group UART Interface P1.2/TXD Output, Transmit data from IRMCF171 P1.1/RXD Input, Receive data to IRMCF171 Discrete I/O Interface P1.0/T2 Input/output port 1.0, can be configured as Timer/Counter 2 input P1.1/RXD Input/output port 1.1, can be configured as RXD input P1.2/TXD Input/output port 1.2, can be configured as TXD output P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock output P1.4/CAP Input/output port 1.4, can be configured as Capture Timer input P1.5 Input/output port 1.5 P2.0/NMI Input/output port 2.0, can be configured as non-maskable interrupt input P2.7/AOPWM1 Input/output port 2.7, can be configured as AOPWM1 output P3.0/INT2/CS1 Input/output port 3.0, can be configured as INT2 input or SPI chip select 1 P3.1/AOPWM2 Input/output port 3.1, can be configured as AOPWM2 output P3.2/NINT0 Input/output port 3.2, can be configured as INT0 input P3.3/NINT1 Input/output port 3.3, can be configured as INT1 input P5.1/TDI Input port 5.1, configured as JTAG port by default |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
