AFE5812ZCF datasheet(58/109 Pages) TI

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AFE5812

SLOS816A – MARCH 2015 – REVISED MARCH 2015

www.ti.com

Address

Default

Function

Description

(DEC)

(HEX)

Value

52[7:6]

0x34[7:6]

PRESET_ACTIVE_ TERMINATIONS

00: 50

01: 100

10: 200

11: 400

Note: The device adjusts resistor mapping

(52[4:0]) automatically. 50-

Ω active termination is

not supported in 15-dB LNA setting. Instead, 00

represents high-impedance mode when LNA gain

is 15 dB.

52[8]

0x34[8]

ACTIVE TERMINATION ENABLE

0: Disable

1: Enable active termination

52[10:9]

0x34[10:9]

LNA_INPUT_CLAMP_SETTING

00: Auto setting

01: 1.5 Vpp

10: 0.825 Vpp

11: 0.6 Vpp

52[11]

0x34[11]

RESERVED

Set to 0

52[12]

0x34[12]

LNA_INTEGRATOR_DISABLE

0: Enable

(LNA_HPF_DISABLE)

1: Disable offset integrator for LNA. See the

explanation for this function in the following

section

52[14:13]

0x34[14:13]

LNA_GAIN

00: 18 dB

01: 24 dB

10: 15 dB

11: Reserved

52[15]

0x34[15]

LNA_INDIVIDUAL_CH_CNTL

0: Disable

1: Enable LNA individual channel control. See

53[7:0]

0x35[7:0]

VCA_PDN_CH<7:0>

0: Normal operation

1: Powers down corresponding channels. Bit7

→

CH8, Bit6

→ CH7…Bit0 → CH1. PDN_CH shuts

down whichever blocks are active depending on

TGC mode or CW mode.

53[8]

0x35[8]

RESERVED

Set to 0

53[9]

0x35[9]

LOW_NF

0: Normal operation

1: Enable low-noise figure mode for high-

impedance probes

53[11:10]

0x35[11:10]

POWER_MODES

00: Low noise mode

01: Set to low-power mode. At 30-dB PGA, total

chain gain may slightly change. See Typical

Characteristics.

10: Set to medium-power mode. At 30-dB PGA,

total chain gain may slightly change. See Typical

Characteristics.

11: Reserved

53[12]

0x35[12]

PDN_VCAT_PGA

0: Normal operation

1: Powers down VCAT and PGA

53[13]

0x35[13]

PDN_LNA

0: Normal operation

1: Powers down LNA only

53[14]

0x35[14]

VCA_PARTIAL_PDN

0: Normal operation

1: Powers down LNA, VCAT, and PGA partially

(fast-wake response)

53[15]

0x35[15]

VCA_COMPLETE_PDN

0: Normal operation

1: Power down LNA, VCAT, and PGA completely

(slow-wake response). This bit can overwrite

53[14].

54[4:0]

0x36[4:0]

CW_SUM_AMP_GAIN_CNTL

Select feedback resistor for the CW amplifier as

per Table 7

54[5]

0x36[5]

CW_16X_CLK_SEL

0: Accept differential clock

1: Accept CMOS clock

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