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AFE5812ZCF Datasheet(PDF) 13 Page - Texas Instruments |
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AFE5812ZCF Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 109 page  AFE5812 www.ti.com SLOS816A – MARCH 2015 – REVISED MARCH 2015 Electrical Characteristics (continued) AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1 µF at INP and bypassed to ground with 15 nF at INM, No active termination, VCNTL = 0 V, ƒIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65 MSPS, LPF Filter = 15 MHz, low-noise mode, VOUT = –1 dBFS, Single-ended VCNTL mode, VCNTLM = GND, ADC configured in internal reference mode, internal 500- Ω CW feedback resistor, CMOS CW clocks, at ambient temperature, TA = 25°C, Digital demodulator is disabled unless otherwise noted. Min and max values are specified across full-temperature range with AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VREF_IN voltage 1.4 V External reference mode VREF_IN current 50 µA ADC input full-scale range 2 Vpp LVDS rate 65 MSPS at 14 bit 910 Mbps POWER DISSIPATION AVDD voltage 3.15 3.3 3.6 V AVDD_ADC voltage 1.7 1.8 1.9 V AVDD_5V voltage 4.75 5 5.5 V DVDD voltage 1.7 1.8 1.9 V TGC low-noise mode, 65 MSPS 180 214 TGC low-noise mode, 40 MSPS 163 Total power dissipation per channel mW/CH TGC medium-power mode, 40 MSPS 125 TGC low-power mode, 40 MSPS 109 TGC low-noise mode, no signal 108 130 TGC medium-power mode, no signal 68 TGC low-power mode, no signal 59 CW-mode, no signal, 16x clock = 80MHz 49 AVDD (3.3-V) current mA TGC low-noise mode, 500 mVPP Input,1% duty cycle 116 TGC medium-power mode, 500 mVPP Input, 1% duty cycle 75 TGC low power, 500 mVPP Input, 1% duty cycle 65 CW-mode, 500 mVPP Input to all 8 channels 281 TGC mode no signal 116 140 CW mode no signal, 16× clock = 80 MHz 139 AVDD_5V current mA TGC mode, 500 mVpp Input,1% duty cycle 116.5 CW-mode, 500 mVpp input 148 TGC low-noise mode, no signal 117 142 TGC medium-power mode, no signal 79 TGC low-power mode, no signal 63 VCA power dissipation mW/CH TGC low-noise mode, 500 mVPP input,1% duty cycle 121 TGC medium-power mode, 500 mVPP Input, 1% duty cycle 82 TGC low-power mode, 500 mVpp input,1% duty cycle 67 No signal, ADC shutdown CW mode no signal, 16× clock = 80 MHz 107 CW power dissipation mW/CH 500 mVPP input, ADC shutdown , 16× clock = 80 MHz 209 AVDD_ADC (1.8-V) current 65MSPS 187 220 mA DVDD (1.8-V) current 65 MSPS 90 110 mA 65 MSPS 59 69 50 MSPS 51 ADC power dissipation/CH mW/CH 40 MSPS 46 20 MSPS 35 PDN_VCA = High, PDN_ADC = High 25 Power dissipation in power down mode mW/CH Complete power-down PDN_Global = High 0.675 Power-down response time Time taken to enter power down 1 µs 2 µs + 1% of VCA power down PDN time µs Power-up response time ADC power down 1 Complete power down 2.5 ms FIN = 5 MHz, at 50 mVPP noise at 1 kHz on supply (4) –65 dBc Power supply modulation ratio, AVDD and AVDD_5V FIN = 5 MHz, at 50 mVpp noise at 50 kHz on supply (4) –65 (4) PSMR specification is with respect to carrier signal amplitude. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: AFE5812 |
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