AFE5812ZCF datasheet(65/109 Pages) TI

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AFE5812

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SLOS816A – MARCH 2015 – REVISED MARCH 2015

Table 12. Digital Demodulator Register Map(1)(2)(3) (continued)

Address

(HEX)

(DEC)

Default

Description

BIT [5:0]

0 = Enable first-order digital HPF. –3 dB cut off frequency is at 0.0225

× Fs / 2. Its transfer function equation is h(n) = a / b, where a = [1 –

DHPF

0A[12]

10[12]

7569 / 213] and b = [1 –1];

1 = Disable first-order digital HPF.

Swap channel pairs. It is used in 4 LVDS bypass configuration to

OUTPUT_CHANNEL_SEL

0A[11]

10[11]

select which of the two possible data streams to pass on. See

Table 11.

SIN_COS_RESET_ON_TX

0 = Continuous phase

0A[10]

10[10]

_TRIG

1 = Reset down conversion phase on TX_TRIG

0 = Use 4 LVDS lines (1, 3, 5, 7)

FULL_LVDS_MODE

0A[9]

10[9]

1 = Use 8 LVDS lines (1 through 8)

Note: 4 LVDS mode valid only for decimation factors

≥4. See Table 14.

RESERVED

0A[8:5]

10[8:5]

Must set to 0

RESERVED

0A[4]

10[4]

Must set to 1

0 = Enable decimation filter

DEC_BYPASS

0A[3]

10[3]

1 = Bypass decimation filter

0 = Enable down conversion block

DWN_CNV_BYPASS

0A[2]

10[2]

1 = Bypass down conversion block. Note: the decimation filter can still

be used when the down conversion block is bypassed.

RESERVED

0A[1]

10[1]

Must set to 1

0 = Enable DC removal block

DC_REMOVAL_BYPASS

0A[0]

10[0]

1 = Bypass DC removal block

LVDS sync word. When MODULATE_BYPASS = 1, there is no sync

SYNC_WORD

0B[15:0]

11[15:0]

0x2772

word output.

Profile word selector.

The Profile Index register is a special 5-bit data register. Read value

PROFILE_INDX

0E[15:11]

14[15:11]

still uses 16-bit convention, which means data will be available on LSB

0e[4:0])

54[13:0]

→ DC offset for channel 1, SCID1_SEL,SCID0_SEL = 01

94[13:0]

→ DC offset for channel 5, SCID1_SEL,SCID0_SEL = 10

Note: Considering the CH-to-CH DC offset variation, the offset value

DC_REMOVAL_1_5

14[13:0]

20[13:0]

must be set individually. Therefore, SCID1_SEL,SCID0_SEL should

not be set as 11.

Note: DC_REMOVAL_X_X registers are write-only.

55[13:0]

→ DC offset for channel 2, SCID1_SEL,SCID0_SEL = 01

95[13:0]

→ DC offset for channel 6, SCID1_SEL,SCID0_SEL = 10

Note: Considering the CH-to-CH DC offset variation, the offset value

DC_REMOVAL_2_6

15[13:0]

21[13:0]

must be set individually. Therefore, SCID1_SEL,SCID0_SEL should

not be set as 11.

Note: DC_REMOVAL_X_X registers are write-only.

56[13:0]

→ DC offset for channel 3, SCID1_SEL,SCID0_SEL=01

96[13:0]

→ DC offset for channel 7, SCID1_SEL,SCID0_SEL=10

Note: Considering the CH-to-CH DC offset variation, the offset value

DC_REMOVAL_3_7

16[13:0]

22[13:0]

must be set individually. Therefore, SCID1_SEL,SCID0_SEL should

not be set as 11.

Note: DC_REMOVAL_X_X registers are write-only.

57[13:0]

→ DC offset for channel 4, SCID1_SEL,SCID0_SEL = 01

97[13:0]

→ DC offset for channel 8, SCID1_SEL,SCID0_SEL = 10

Note: Considering the CH-to-CH DC offset variation, the offset value

DC_REMOVAL_4_8

17[13:0]

23[13:0]

must be set individually. Therefore, SCID1_SEL,SCID0_SEL should

not be set as 11.

Note: DC_REMOVAL_X_X registers are write-only.

0 = Profile vector specifies the number of bit to shift for the decimation

filter output.

DEC_SHIFT_FORCE_EN

1D[7]

29[7]

1 = Register 1D[6:4] specifies the number of bit to shift for the

decimation filter output.

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