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AM1806 Datasheet(PDF) 140 Page - Texas Instruments |
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AM1806 Datasheet(HTML) 140 Page - Texas Instruments |
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140 / 245 page ![]() 2 1 CLKS FSRexternal CLKR/X(noneedtoresync) CLKR/X(needsresync) Bit(n1) (n2) (n3) Bit0 Bit(n1) (n2) (n3) 14 12 11 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 CLKS CLKR FSR(int) FSR(ext) DR CLKX FSX(int) FSX(ext) FSX(XDATDLY=00b) DX 13 (A) 13 (A) AM1806 SPRS658F – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com A. No. 13 applies to the first data bit only when XDATDLY ≠ 0. Figure 6-31. McBSP Timing Table 6-58. Timing Requirements for McBSP0 FSR When GSYNC = 1 (see Figure 6-32) 1.3V, 1.2V 1.1V 1.0V NO. UNIT MIN MAX MIN MAX MIN MAX 1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 4 4.5 5 ns 2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 4 4 ns Table 6-59. Timing Requirements for McBSP1 FSR When GSYNC = 1 (see Figure 6-32) 1.3V, 1.2V 1.1V 1.0V NO. UNIT MIN MAX MIN MAX MIN MAX 1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 5 5 10 ns 2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 4 4 ns Figure 6-32. FSR Timing When GSYNC = 1 140 Peripheral Information and Electrical Specifications Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM1806 |
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