AM1806 datasheet(144/245 Pages) TI

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AM1806

SPRS658F – FEBRUARY 2010 – REVISED MARCH 2014

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6.16.2 SPI Electrical Data/Timing

6.16.2.1 Serial Peripheral Interface (SPI) Timing

Table 6-61 through Table 6-76 assume testing over recommended operating conditions (see Figure 6-35

through Figure 6-38).

Table 6-61. General Timing Requirements for SPI0 Master Modes(1)

1.3V, 1.2V

1.1V

1.0V

NO.

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tc(SPC)M

Cycle Time, SPI0_CLK, All Master Modes

20(2)

256P

30(2)

256P

40(2)

256P

tw(SPCH)M

Pulse Width High, SPI0_CLK, All Master Modes

0.5M-1

tw(SPCL)M

Pulse Width Low, SPI0_CLK, All Master Modes

0.5M-1

Polarity = 0, Phase = 0,

to SPI0_CLK rising

Polarity = 0, Phase = 1,

-0.5M+5

-0.5M+6

Delay, initial data bit valid on

to SPI0_CLK rising

td(SIMO_SPC)M

SPI0_SIMO after initial edge

Polarity = 1, Phase = 0,

on SPI0_CLK(3)

to SPI0_CLK falling

Polarity = 1, Phase = 1,

-0.5M+5

-0.5M+6

to SPI0_CLK falling

Polarity = 0, Phase = 0,

from SPI0_CLK rising

Polarity = 0, Phase = 1,

Delay, subsequent bits valid

from SPI0_CLK falling

td(SPC_SIMO)M

on SPI0_SIMO after transmit

Polarity = 1, Phase = 0,

edge of SPI0_CLK

from SPI0_CLK falling

Polarity = 1, Phase = 1,

from SPI0_CLK rising

Polarity = 0, Phase = 0,

0.5M-3

from SPI0_CLK falling

Polarity = 0, Phase = 1,

0.5M-3

Output hold time, SPI0_SIMO

from SPI0_CLK rising

toh(SPC_SIMO)M

valid after receive edge of

Polarity = 1, Phase = 0,

SPI0_CLK

0.5M-3

from SPI0_CLK rising

Polarity = 1, Phase = 1,

0.5M-3

from SPI0_CLK falling

Polarity = 0, Phase = 0,

1.5

to SPI0_CLK falling

Polarity = 0, Phase = 1,

1.5

Input Setup Time, SPI0_SOMI

to SPI0_CLK rising

tsu(SOMI_SPC)M

valid before receive edge of

Polarity = 1, Phase = 0,

SPI0_CLK

1.5

to SPI0_CLK rising

Polarity = 1, Phase = 1,

1.5

to SPI0_CLK falling

Polarity = 0, Phase = 0,

from SPI0_CLK falling

Polarity = 0, Phase = 1,

Input Hold Time, SPI0_SOMI

from SPI0_CLK rising

tih(SPC_SOMI)M

valid after receive edge of

Polarity = 1, Phase = 0,

SPI0_CLK

from SPI0_CLK rising

Polarity = 1, Phase = 1,

from SPI0_CLK falling

(1)

P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)

(2)

This timing is limited by the timing shown or 3P, whichever is greater.

(3)

First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on

SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.

144

Peripheral Information and Electrical Specifications

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