AM1806 datasheet(156/245 Pages) TI

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AM1806

SPRS658F – FEBRUARY 2010 – REVISED MARCH 2014

www.ti.com

Table 6-75. Additional(1) SPI1 Slave Timings, 4-Pin Chip Select Option(2)(3) (continued)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Polarity = 0, Phase = 0,

0.5M+P+4

0.5M+P+5

0.5M+P+6

from SPI1_CLK falling

Polarity = 0, Phase = 1,

P+4

P+5

P+6

from SPI1_CLK falling

Required delay from final SPI1_CLK edge

td(SPC_SCSH)S

before SPI1_SCS is deasserted.

Polarity = 1, Phase = 0,

0.5M+P+4

0.5M+P+5

0.5M+P+6

from SPI1_CLK rising

Polarity = 1, Phase = 1,

P+4

P+5

P+6

from SPI1_CLK rising

tena(SCSL_SOMI)S

Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid

P+15

P+17

P+19

tdis(SCSH_SOMI)S

Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI

P+15

P+17

P+19

156

Peripheral Information and Electrical Specifications

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