AM1806 datasheet(157/245 Pages) TI

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AM1806

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SPRS658F – FEBRUARY 2010 – REVISED MARCH 2014

Table 6-76. Additional(1) SPI1 Slave Timings, 5-Pin Option(2)(3)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Required delay from SPI1_SCS asserted at slave to

td(SCSL_SPC)S

P+1.5

first SPI1_CLK edge at slave.

Polarity = 0, Phase = 0,

0.5M+P+4

0.5M+P+5

0.5M+P+6

from SPI1_CLK falling

Polarity = 0, Phase = 1,

P+4

P+5

P+6

Required delay from final

from SPI1_CLK falling

td(SPC_SCSH)S

SPI1_CLK edge before

Polarity = 1, Phase = 0,

SPI1_SCS is deasserted.

0.5M+P+4

0.5M+P+5

0.5M+P+6

from SPI1_CLK rising

Polarity = 1, Phase = 1,

P+4

P+5

P+6

from SPI1_CLK rising

tena(SCSL_SOMI)

Delay from master asserting SPI1_SCS to slave

P+15

P+17

P+19

driving SPI1_SOMI valid

Delay from master deasserting SPI1_SCS to slave 3-

tdis(SCSH_SOMI)S

P+15

P+17

P+19

stating SPI1_SOMI

Delay from master deasserting SPI1_SCS to slave

tena(SCSL_ENA)S

driving SPI1_ENA valid

Polarity = 0, Phase = 0,

2.5P+15

2.5P+17

2.5P+19

from SPI1_CLK falling

Polarity = 0, Phase = 1,

Delay from final clock

2.5P+15

2.5P+17

2.5P+19

from SPI1_CLK rising

receive edge on SPI1_CLK

tdis(SPC_ENA)S

to slave 3-stating or driving

Polarity = 1, Phase = 0,

2.5P+15

2.5P+17

2.5P+19

high SPI1_ENA.(4)

from SPI1_CLK rising

Polarity = 1, Phase = 1,

2.5P+15

2.5P+17

2.5P+19

from SPI1_CLK falling

(1)

These parameters are in addition to the general timings for SPI slave modes (Table 6-70).

(2)

P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

(4)

SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-

stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying

several SPI slave devices to a single master.

Peripheral Information and Electrical Specifications

157

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