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AM1806 Datasheet(PDF) 200 Page - Texas Instruments

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Part # AM1806
Description  AM1806 ARM짰 Microprocessor
PDF  245 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM1806 Datasheet(HTML) 200 Page - Texas Instruments

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AM1806
SPRS658F – FEBRUARY 2010 – REVISED MARCH 2014
www.ti.com
6.22.2 uPP Electrical Data/Timing
Table 6-94. Timing Requirements for uPP (see Figure 6-61, Figure 6-62, Figure 6-63, Figure 6-64)
1.3V, 1.2V
1.1V
1.0V
NO.
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
SDR mode
13.33
20
26.66
1
tc(INCLK)
Cycle time, CHn_CLK
ns
DDR mode
26.66
40
53.33
SDR mode
5
8
10
2
tw(INCLKH)
Pulse width, CHn_CLK high
ns
DDR mode
10
16
20
SDR mode
5
8
10
3
tw(INCLKL)
Pulse width, CHn_CLK low
ns
DDR mode
10
16
20
4
tsu(STV-INCLKH)
Setup time, CHn_START valid before CHn_CLK high
4
5.5
6.5
ns
5
th(INCLKH-STV)
Hold time, CHn_START valid after CHn_CLK high
0.8
0.8
0.8
ns
6
tsu(ENV-INCLKH)
Setup time, CHn_ENABLE valid before CHn_CLK high
4
5.5
6.5
ns
7
th(INCLKH-ENV)
Hold time, CHn_ENABLE valid after CHn_CLK high
0.8
0.8
0.8
ns
Setup time, CHn_DATA/XDATA valid before CHn_CLK
8
tsu(DV-INCLKH)
4
5.5
6.5
ns
high
9
th(INCLKH-DV)
Hold time, CHn_DATA/XDATA valid after CHn_CLK high
0.8
0.8
0.8
ns
Setup time, CHn_DATA/XDATA valid before CHn_CLK
10
tsu(DV-INCLKL)
4
5.5
6.5
ns
low
11
th(INCLKL-DV)
Hold time, CHn_DATA/XDATA valid after CHn_CLK low
0.8
0.8
0.8
ns
19
tsu(WTV-INCLKL)
Setup time, CHn_WAIT valid before CHn_CLK high
10
12
14
ns
20
th(INCLKL-WTV)
Hold time, CHn_WAIT valid after CHn_CLK high
0.8
0.8
0.8
ns
21
tc(2xTXCLK)
Cycle time, 2xTXCLK input clock(1)
6.66
10
13.33
ns
(1)
2xTXCLK is an alternate transmit clock source that must be at least 2 times the required uPP transmit clock rate (as it is is divided down
by 2 inside the uPP). 2xTXCLK has no specified skew relationship to the CHn_CLOCK and therefore is not shown in the timing diagram.
Table 6-95. Switching Characteristics Over Recommended Operating Conditions for uPP
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
SDR mode
13.33
20
26.66
12
tc(OUTCLK)
Cycle time, CHn_CLK
ns
DDR mode
26.66
40
53.33
SDR mode
5
8
10
13
tw(OUTCLKH)
Pulse width, CHn_CLK high
ns
DDR mode
10
16
20
SDR mode
5
8
10
14
tw(OUTCLKL)
Pulse width, CHn_CLK low
ns
DDR mode
10
16
20
15
td(OUTCLKH-STV)
Delay time, CHn_START valid after CHn_CLK high
2
11
2
15
2
21
ns
16
td(OUTCLKH-ENV)
Delay time, CHn_ENABLE valid after CHn_CLK high
2
11
2
15
2
21
ns
17
td(OUTCLKH-DV)
Delay time, CHn_DATA/XDATA valid after CHn_CLK high
2
11
2
15
2
21
ns
18
td(OUTCLKL-DV)
Delay time, CHn_DATA/XDATA valid after CHn_CLK low
2
11
2
15
2
21
ns
200
Peripheral Information and Electrical Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
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