AM1806 datasheet(203/245 Pages) TI

203 / 245 page

AM1806

www.ti.com

SPRS658F – FEBRUARY 2010 – REVISED MARCH 2014

6.23 Video Port Interface (VPIF)

The Video Port Interface (VPIF) allows the capture and display of digital video streams. Features include:

•

Up to 2 Video Capture Channels (Channel 0 and Channel 1)

–

Two 8-bit Standard-Definition (SD) Video with embedded timing codes (BT.656)

–

Single 16-bit High-Definition (HD) Video with embedded timing codes (BT.1120)

–

Single Raw Video (8-/10-/12-bit)

•

Up to 2 Video Display Channels (Channel 2 and Channel 3)

–

Two 8-bit SD Video Display with embedded timing codes (BT.656)

–

Single 16-bit HD Video Display with embedded timing codes (BT.1120)

The VPIF capture channel input data format is selectable based on the settings of the specific Channel

Control Register (Channels 0–3). The VPIF Raw Video data-bus width is selectable based on the settings

of the Channel 0 Control Register.

6.23.1 VPIF Register Descriptions

Table 6-96 shows the VPIF registers.

Table 6-96. Video Port Interface (VPIF) Registers

BYTE ADDRESS

ACRONYM

0x01E1 7000

PID

Peripheral identification register

0x01E1 7004

CH0_CTRL

Channel 0 control register

0x01E1 7008

CH1_CTRL

Channel 1 control register

0x01E1 700C

CH2_CTRL

Channel 2 control register

0x01E1 7010

CH3_CTRL

Channel 3 control register

0x01E1 7014 - 0x01E1 701F

Reserved

0x01E1 7020

INTEN

Interrupt enable

0x01E1 7024

INTENSET

Interrupt enable set

0x01E1 7028

INTENCLR

Interrupt enable clear

0x01E1 702C

INTSTAT

Interrupt status

0x01E1 7030

INTSTATCLR

Interrupt status clear

0x01E1 7034

EMU_CTRL

Emulation control

0x01E1 7038

DMA_SIZE

DMA size control

0x01E1 703C - 0x01E1 703F

Reserved

CAPTURE CHANNEL 0 REGISTERS

0x01E1 7040

CH0_TY_STRTADR

Channel 0 Top Field luma buffer start address

0x01E1 7044

CH0_BY_STRTADR

Channel 0 Bottom Field luma buffer start address

0x01E1 7048

CH0_TC_STRTADR

Channel 0 Top Field chroma buffer start address

0x01E1 704C

CH0_BC_STRTADR

Channel 0 Bottom Field chroma buffer start address

0x01E1 7050

CH0_THA_STRTADR

Channel 0 Top Field horizontal ancillary data buffer start address

0x01E1 7054

CH0_BHA_STRTADR

Channel 0 Bottom Field horizontal ancillary data buffer start address

0x01E1 7058

CH0_TVA_STRTADR

Channel 0 Top Field vertical ancillary data buffer start address

0x01E1 705C

CH0_BVA_STRTADR

Channel 0 Bottom Field vertical ancillary data buffer start address

0x01E1 7060

CH0_SUBPIC_CFG

Channel 0 sub-picture configuration

0x01E1 7064

CH0_IMG_ADD_OFST

Channel 0 image data address offset

0x01E1 7068

CH0_HA_ADD_OFST

Channel 0 horizontal ancillary data address offset

0x01E1 706C

CH0_HSIZE_CFG

Channel 0 horizontal data size configuration

0x01E1 7070

CH0_VSIZE_CFG0

Channel 0 vertical data size configuration (0)

0x01E1 7074

CH0_VSIZE_CFG1

Channel 0 vertical data size configuration (1)

0x01E1 7078

CH0_VSIZE_CFG2

Channel 0 vertical data size configuration (2)

0x01E1 707C

CH0_VSIZE

Channel 0 vertical image size

Peripheral Information and Electrical Specifications

203

Submit Documentation Feedback

Product Folder Links: AM1806

AM1806 Datasheet(PDF) 203 Page - Texas Instruments

AM1806 Datasheet(HTML) 203 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL