DM385 datasheet(131/281 Pages) TI

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DM385, DM388

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SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

Table 7-3. Device Operating Points (OPPs)

CORE LOGIC VOLTAGE DOMAINS

ARM

HDVICP2

CORE

L3/L4,

Cortex A8

HDVPSS

ISS

Media Ctlr.

DDR

OPP

HDVICP2

Core

(MHz)

(MHz)(1)

(MHz)

100%(1.1 V)

600

220

200

400

200

400

(AAR0x)(2)

120% (1.2 V)

720

290

200

400

200

400

(AAR0x)

Turbo (1.35 V)

970

410

240

480

240

533

(AAR1x)

Nitro (1.35 V)

1000

450

260

560

280

240

533

(AAR2x)

(1)

All DDR access must be suspended prior to changing the DDR frequency of operation.

(2)

OPP100 is currently supported only on DM388 commercial temperature devices.

Although the OPP for each Core Logic Voltage Domain is independently selectable, not all combinations

of OPPs are supported. Table 7-4 marks the supported ARM OPPs for a given CORE OPP.

Table 7-4. Supported OPP Combinations(1)

ARM

HDVICP2

CORE

Nitro

Turbo

OPP120

OPP100(2)

Nitro

Turbo

OPP120

OPP100(2)

Nitro

Turbo

OPP120

OPP100(2)

(1)

"X" denotes supported combinations.

(2)

OPP100 is currently only supported on DM388 commercial temperature devices.

7.2.2.2

Adaptive Voltage Scaling [Currently Not Supported]

As mentioned in Section 7.2.2.1, Dynamic Voltage Frequency Scaling (DVFS) above, every OPP has an

associated voltage range. Based on the silicon process, temperature, and chosen OPP, the SmartReflex

modules guide software in adjusting the Core Logic Voltage Domain supply voltage (CVDD) within these

ranges. This technique is called Adaptive Voltage Scaling (AVS). AVS occurs continuously and in real-

time, helping to minimize power consumption in response to changing operating conditions.

7.2.3

Memory Power Management

In order to reduce SRAM leakage, many SRAM blocks can be switched from ACTIVE mode to

SHUTDOWN mode. When SRAM is put in SHUTDOWN mode, the voltage supplied to it is automatically

removed and all data in that SRAM is lost.

All SRAM located in a switchable power domain (all domains except ALWAYS_ON) automatically enters

SHUTDOWN mode whenever its associated power domain goes into the "OFF" state. The SRAM returns

to the ACTIVE state when the corresponding Power Domain returns to the "ON" state.

In addition, the following SRAM within the ALWAYS_ON Power Domain can also be independently put

into SHUTDOWN by programming the x_MEM_PWRDN registers in the Control Module:

•

Media Controller SRAM

•

OCMC SRAM

7.2.4

SERDES_CLKP/N LDO

The SERDES_CLKP/N input buffers are powered by an internal LDO which is programmed through the

REFCLK_LJCBLDO_CTRL register in the Control Module.

Power, Reset, Clocking, and Interrupts

131

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