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DM385 Datasheet(PDF) 134 Page - Texas Instruments |
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DM385 Datasheet(HTML) 134 Page - Texas Instruments |
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134 / 281 page ![]() POR CVDD CVDD_x 3.3 V Supplies (DVDD, DVDD_x, VDDA_x_3P3) 1.8 V Supplies (DVDD, DVDD_x, VDDA_x_1P8, VDDA_1P8) 1 4 3 1.35 V/1.5 V/1.8 V DVDD_DDR[0] 2 DM385, DM388 SPRS821D – MARCH 2013 – REVISED DECEMBER 2013 www.ti.com Both 1.8 V and DVDD_DDR[x] supplies must be powered up and stable prior to starting the ramp of the 3.3 V supplies. CVDD powered-up coincidently or prior to CVDD_ARM and CVDD_HDVICP supplies. Figure 7-1. Power-Up Sequence 7.2.8.2 Power-Down Sequence For proper device operation, the following power-down sequence in Table 7-6, Figure 7-2, Figure 7-3, and Figure 7-4 must be followed. Table 7-6. Power-Down Sequence Ramping Values NO. DESCRIPTION MIN MAX UNIT 5 CVDD, CVDD_x variable supplies to 1.8 V supplies 0 ms 6 1.35-/1.5-/1.8-V DVDD_DDR[x] supplies to 1.8 V supplies 0 ms 7 3.3 V supplies to 1.8 V supplies (1) (1) ms 8 CVDD_x supplies to CVDD supply (2) (2) ms (1) The 3.3 V supplies must never be more than 2 V above the 1.8 V supplies (see Figure 7-3). (2) The CVDD supply must be powered down coincidentally or after CVDD_ARM and CVDD_HDVICP supplies (see Figure 7-4). 134 Power, Reset, Clocking, and Interrupts Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DM385 DM388 |
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