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DM385 Datasheet(PDF) 220 Page - Texas Instruments |
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DM385 Datasheet(HTML) 220 Page - Texas Instruments |
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220 / 281 page ![]() DDR[0]_D[0] DDR[0]_D[7] DDR[0]_DQM[0] DDR[0]_DQS[0] DDR[0]_DQS[0] DDR[0]_D[8] DDR[0]_D[15] DDR[0]_DQM[1] DDR[0]_DQS[1] DDR[0]_DQS[1] DQ0 DQ7 LDM LDQS LDQS DQ8 DQ15 UDM UDQS UDQS BA0 BA2 A0 A15 CS CAS RAS WE CKE CK CK VREF DDR[0]_D[16] DDR[0]_D[23] DDR[0]_DQM[2] DDR[0]_DQS[2] DDR[0]_DQS[2] DDR[0]_D[24] DDR[0]_D[31] DDR[0]_DQM[3] DDR[0]_DQS[3] DDR[0]_DQS[3] DDR[0]_BA[0] DDR[0]_BA[2] DDR[0]_A[0] DDR[0]_A[15] DDR[0]_CS[0] DDR[0]_CAS DDR[0]_RAS DDR[0]_WE DDR[0]_CKE DDR[0]_CLK DDR[0]_CLK VREFSSTL_DDR[0] 1 K 1% Vio 1.8 (A) DDR2 VREF 0.1 µF VREF 0.1 µF 1 K 1% 0.1 µF (B) 0.1 µF (B) ODT NC NC NC 1 K NC NC 1 K 1 K 1 K DDR[0]_VTP 50 ( 2%) ± Vio 1.8 (A) Vio 1.8 (A) T0 T0 T0 T0 T0 T0 T0 T0 T0 T0 T0 T0 T0 Termination is required. See terminator comments. DDR[0]_ODT[0] DDR[0]_RST NC NC DM385, DM388 SPRS821D – MARCH 2013 – REVISED DECEMBER 2013 www.ti.com A. Vio1.8 is the power supply for the DDR2 memories and the device DDR2 interface. B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin. Figure 8-49. 16-Bit DDR2 High-Level Schematic 220 Peripheral Information and Timings Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DM385 DM388 |
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