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DM385 Datasheet(PDF) 222 Page - Texas Instruments |
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DM385 Datasheet(HTML) 222 Page - Texas Instruments |
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222 / 281 page ![]() DM385, DM388 SPRS821D – MARCH 2013 – REVISED DECEMBER 2013 www.ti.com Complete stackup specifications are provided in Table 8-50. Table 8-50. PCB Stackup Specifications NO. PARAMETER MIN TYP MAX UNIT 1 PCB routing/plane layers 6 2 Signal routing layers 3 3 Full ground layers under DDR2 routing region 2 4 Number of ground plane cuts allowed within DDR routing region 0 5 Number of ground reference planes required for each DDR2 routing layer 1 6 Number of layers between DDR2 routing layer and reference ground plane 0 7 PCB feature spacing 4 Mils 8 PCB trace width, w 4 Mils 9 PCB BGA escape via pad size(1) 18 20 Mils 10 PCB BGA escape via hole size(1) 10 Mils 11 Processor BGA pad size 0.4 mm 13 Single-ended impedance, Zo 50 75 Ω 14 Impedance control(2) Z-5 Z Z+5 Ω (1) A 20/10 via may be used if enough power routing resources are available. An 18/10 via allows for more flexible power routing to the processor. (2) Z is the nominal singled-ended impedance selected for the PCB specified by item 13. 222 Peripheral Information and Timings Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DM385 DM388 |
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