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DM385 Datasheet(PDF) 241 Page - Texas Instruments |
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DM385 Datasheet(HTML) 241 Page - Texas Instruments |
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241 / 281 page  A1 A2 Processor Address and Control Output Buffer DDR Address and Control Input Buffers A3 AT Vtt Address and Control Terminator Rtt A1 A2 Processor Differential Clock Output Buffer DDR Differential CK Input Buffers Routed as Differential Pair A3 AT Rcp Clock Parallel Terminator A1 A2 A3 AT Rcp Cac DVDD_DDR[0] 0.1 µF + – + – + – DM385, DM388 www.ti.com SPRS821D – MARCH 2013 – REVISED DECEMBER 2013 Figure 8-66. CK Topology for Two DDR3 Devices Figure 8-67. ADDR_CTRL Topology for Two DDR3 Devices 8.13.3.14.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices Figure 8-68 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 8-69 shows the corresponding ADDR_CTRL routing. Copyright © 2013, Texas Instruments Incorporated Peripheral Information and Timings 241 Submit Documentation Feedback Product Folder Links: DM385 DM388 |
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