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DM385 Datasheet(PDF) 244 Page - Texas Instruments |
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DM385 Datasheet(HTML) 244 Page - Texas Instruments |
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244 / 281 page  A1 A2 Processor Address and Control Output Buffer DDR Address and Control Input Buffers AT Vtt Address and Control Terminator Rtt A1 A2 Processor Differential Clock Output Buffer DDR Differential CK Input Buffer Routed as Differential Pair AT Rcp Clock Parallel Terminator A1 A2 AT Rcp Cac DVDD_DDR[0] 0.1 µF + – + – DM385, DM388 SPRS821D – MARCH 2013 – REVISED DECEMBER 2013 www.ti.com Figure 8-72. CK Topology for One DDR3 Device Figure 8-73. ADDR_CTRL Topology for One DDR3 Device 8.13.3.14.3.2 CK and ADDR/CTRL Routing, One DDR3 Device Figure 8-74 shows the CK routing for one DDR3 device placed on the same side of the PCB. Figure 8-75 shows the corresponding ADDR_CTRL routing. 244 Peripheral Information and Timings Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DM385 DM388 |
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