DM385 datasheet(247/281 Pages) TI

247 / 281 page

Rtt

Vtt

(A)

CACLMX

CACLMY

DM385, DM388

www.ti.com

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

8.13.3.16 Routing Specification

8.13.3.16.1 CK and ADDR_CTRL Routing Specification

Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this

skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter

traces up to the length of the longest net in the net class and its associated clock. A metric to establish

this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the

length between the points when connecting them only with horizontal or vertical segments. A reasonable

trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address

Control Longest Manhattan distance.

Given the clock and address pin locations on the processor and the DDR3 memories, the maximum

possible Manhattan distance can be determined given the placement. Figure 8-80 and Figure 8-81 show

this distance for four loads and two loads, respectively. It is from this distance that the specifications on

the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly

for other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net

class. For CK and ADDR_CTRL routing, these specifications are contained in Table 8-70.

It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3

memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that

satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.

The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this

length calculation. Non-included lengths are grayed out in the figure.

Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.

The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.

Figure 8-80. CACLM for Four Address Loads on One Side of PCB

Peripheral Information and Timings

247

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DM385 Datasheet(PDF) 247 Page - Texas Instruments