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DM385 Datasheet(PDF) 267 Page - Texas Instruments |
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DM385 Datasheet(HTML) 267 Page - Texas Instruments |
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267 / 281 page  DM385, DM388 www.ti.com SPRS821D – MARCH 2013 – REVISED DECEMBER 2013 8.18 Timers The device has eight 32-bit general-purpose (GP) timers (TIMER8 - TIMER1) that have the following features: • TIMER8, TIMER1 are for software use and do not have an external connection • Dedicated input trigger for capture mode and dedicated output trigger/pulse width modulation (PWM) signal • Interrupts generated on overflow, compare, and capture • Free-running 32-bit upward counter • Supported modes: – Compare and capture modes – Auto-reload mode – Start-stop mode • TIMER[8:1] functional clock is sourced from either the DEVOSC, AUXOSC, AUD_CLK2/1/0, TCLKIN, or SYSCLK18 27 MHz as selected by the timer clock multiplexers. • On-the-fly read/write register (while counting) • Generates interrupts to the ARM and Media Controller. The device has one system watchdog timer that have the following features: • Free-running 32-bit upward counter • On-the-fly read/write register (while counting) • Reset upon occurrence of a timer overflow condition • The system watchdog timer has two possible clock sources: – RCOSC32K oscillator – RTCDIVIDER • The watchdog timer is used to provide a recovery mechanism for the device in the event of a fault condition, such as a non-exiting code loop. For more detailed information on the GP and Watchdog Timers, see the Timers and Watchdog Timer chapters in the device-specific Technical Reference Manual. 8.18.1 Timer Peripheral Register Descriptions The Timer peripheral registers are described in the device-specific Technical Reference Manual. Each register is documented as an offset from a base address for the peripheral. The base addresses for all of the peripherals are in the device memory map (see Section 2.10). Copyright © 2013, Texas Instruments Incorporated Peripheral Information and Timings 267 Submit Documentation Feedback Product Folder Links: DM385 DM388 |
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