October 1998

8-17

MIC8030

MIC8030

Micrel

8

For displays with more than 38 segments, two or more

MIC8030 may be cascaded by connecting DATA OUT of the

previous stage with DATA IN of the next stage; CLOCK,

LOAD and CHIP SELECT of all following stages should be

tied to the control lines of the first MIC8030. The backplane

output of the first stage should be tied to LCD

φ of all following

stages, the LCD

φ OPT must be left unconnected on those

an external 330 k

Ω resistor must be used between the

BACKPLANE of the first stage and LCD

φ of all following

stages.

Packaging options available include DATA OUT 30, 32 or 38

with the corresponding number of segments, and the avail-

ability of LCD

φ OPT. Types of packages include plastic and

ceramic DIPs, surface mount packages, plastic and ceramic

Leadless Chip Carriers and custom packaging.

Pin Configuration

Functional Description

With CHIP SELECT tied low, serial data is clocked into the

shift register at each falling edge of the CLOCK input. Pulling

LOAD high will cause a parallel loading of the shift register

contents into the latches. If load is left high, the latches are

transparent.

A logic “1” clocked into the shift register corresponds to that

segment being on, and that segment is out of phase with the

backplane.

The backplane may be externally driven or the internal

oscillator can be used. If LCD

φ is externally driven, the

backplane will be in phase with the input; LCD

φ OPT is not

connected. The internal oscillator is used by shorting LCD

φ

OPT to LCD

φ, connecting a capacitor to ground, and a

of the input frequency, and is given as: f = 10/[R(C + .0002)]

Example: R = 150 k

Ω, C = 420 pF: f = 108 Hz

7

8

MIC8030-01

9

10

11

12

13

14

15

16

17

Chip Select

Seg 28

Seg 29

Seg 30

Seg 31

Seg 32

SS

V

Seg 17

Seg 16

Seg 15

Seg 14

Seg 13

Seg 12

Seg 11

Seg 10

Seg 9

Seg 8

BB

V

39

38

37

36

35

34

33

32

31

30

29

Clock

Load

Seg 27

Seg 26

44-Pin PLCC (-V)