© 1996 Microchip Technology Inc.

DS21140B-page 3

24LC41

TABLE 1-3:

AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS

PORTS)

DDC Monitor Port (Bi-directional Mode) and Microcontroller Access Port

Parameter

Symbol

Standard Mode

Vcc = 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency (DSCL and

MSCL)

—

100

—

400

kHz

Clock high time (DSCL and

MSCL)

4000

—

600

—

ns

Clock low time (DSCL and

MSCL)

4700

—

1300

—

ns

DSCL, DSDA, MSCL &

MSDA rise time

—

1000

—

300

ns

(Note 1)

DSCL, DSDA, MSCL &

MSDA fall time

—

300

—

300

ns

(Note 1)

START condition hold time

4000

—

600

—

ns

After this period the first

clock pulse is generated

4700

—

600

—

ns

Only relevant for repeated

START condition

Data input hold time

0

—

0

—

ns

(Note 2)

Data input setup time

250

—

100

—

ns

STOP condition setup time

4000

—

600

—

ns

Output valid from clock

—

3500

—

900

ns

(Note 2)

Bus free time

4700

—

1300

—

ns

Time the bus must be free

before a new transmission

can start

—

250

20 + .1

250

ns

≤ 100 pF

Input filter spike suppres-

sion (DSCL, DSDA, MSCL

& MSDA pins)

—

50

—

50

ns

(Note 3)

Write cycle time

—

10

—

10

ms

Byte or Page mode

DDC Monitor Port Transmit-Only Mode Parameters

Output valid from VCLK/

DWP

—

2000

—

1000

ns

VCLK/DWP high time

4000

—

600

—

ns

VCLK/DWP low time

4700

—

1300

—

ns

Mode transition time

—

500

—

500

ns

Transmit-Only power up

time

0—

0

—

ns

Endurance

—

10M

—

10M

—

cycles

25

°C, Vcc = 5.0V, Block

Mode (Note 4)

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of START or STOP

conditions.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific

application, please consult the Total Endurance Model which can be obtained on our BBS or website.