8

FN6213.3

May 6, 2009

Logic input waveform is inverted for switches that have the opposite

logic sense.

capacitance.

FIGURE 1. SWITCHING TIMES

FIGURE 2A. Q MEASUREMENT POINTS

FIGURE 2B. Q TEST CIRCUIT

FIGURE 2. CHARGE INJECTION

capacitance.

FIGURE 3. BREAK-BEFORE-MAKE TIME

50%

90%

3V

0V

LOGIC

INPUT

SWITCH

OUTPUT

10%

0V

VNO0

V

OUT

V

(NO or NC)

R

L

R

L

r

ON

+

------------------------

=

LOGIC

INPUT

ADDA-B

300

Ω

35pF

GND

V+

EN

C

V-

C

V+

C

V-

C

ISL84582

OFF

ON

OFF

Q =

SWITCH

OUTPUT

LOGIC

INPUT

3V

0V

GND

COM

NO OR NC

LOGIC

INPUT

INH

ADDX

V-

C

V+

C

Repeat test for other switches.

1nF

0

Ω

80%

3V

0V

LOGIC

INPUT

SWITCH

OUTPUT

0V

LOGIC

INPUT

ADDA-B

35pF

300

Ω

GND

V+

C

V-

C

V+

C

INH

ISL84582

ISL84582