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LM2744 Datasheet(PDF) 21 Page - Texas Instruments

Part # LM2744
Description  Low Voltage N-Channel MOSFET Synchronous Buck Regulator Controller with External Reference
PDF  33 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LM2744 Datasheet(HTML) 21 Page - Texas Instruments

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GEA = AEA x
s
2SfZ1
+ 1
s
2SfZ2
+ 1
s
2SfP1
+ 1
s
2SfP2
+ 1
s
100
1k
10k
100k
1M
FREQUENCY (Hz)
-60
-44
-28
-12
4
20
100
1k
10k
100k
1M
FREQUENCY (Hz)
-150
-120
-90
-60
-30
0
PVIN x RO
GPS =
VRAMP
sCORC + 1
a x s
2 + b x s + c
x
LM2744
www.ti.com
SNVS292F – SEPTEMBER 2004 – REVISED MARCH 2013
In the equation for fDP, the variable RL is the power stage resistance, and represents the inductor DCR plus the
on resistance of the high-side MOSFET. RO is the output voltage divided by output current. The power stage
transfer function GPS is given by the following equation, and Figure 32 shows Bode plots of the phase and gain in
this example.
(25)
a = LCO(RO + RC)
b = L + CO(RORL + RORC + RCRL)
c = RO + RL
Figure 32. Power Stage Gain and Phase
The double pole at 4.5kHz causes the phase to drop to approximately -130° at around 10kHz. The ESR zero, at
20.3kHz, provides a +90° boost that prevents the phase from dropping to -180º. If this loop were left
uncompensated, the bandwidth would be approximately 10kHz and the phase margin 53°. In theory, the loop
would be stable, but would suffer from poor DC regulation (due to the low DC gain) and would be slow to
respond to load transients (due to the low bandwidth.) In practice, the loop could easily become unstable due to
tolerances in the output inductor, capacitor, or changes in output current, or input voltage. Therefore, the loop is
compensated using the error amplifier and a few passive components.
For this example, a Type III, or three-pole-two-zero approach gives optimal bandwidth and phase.
In most voltage mode compensation schemes, including Type III, a single pole is placed at the origin to boost DC
gain as high as possible. Two zeroes fZ1 and fZ2 are placed at the double pole frequency to cancel the double
pole phase lag. Then, a pole, fP1 is placed at the frequency of the ESR zero. A final pole fP2 is placed at one-half
of the switching frequency. The gain of the error amplifier transfer function is selected to give the best bandwidth
possible without violating the Nyquist stability criteria. In practice, a good crossover point is one-fifth of the
switching frequency, or 60kHz for this example. The generic equation for the error amplifier transfer function is:
(26)
In this equation the variable AEA is a ratio of the values of the capacitance and resistance of the compensation
components, arranged as shown inFigure 32. AEA is selected to provide the desired bandwidth. A starting value
of 80,000 for AEA should give a conservative bandwidth. Increasing the value will increase the bandwidth, but will
also decrease phase margin. Designs with 45-60° are usually best because they represent a good tradeoff
between bandwidth and phase margin. In general, phase margin is lowest and gain highest (worst-case) for
maximum input voltage and minimum output current. One method to select AEA is to use an iterative process
beginning with these worst-case conditions.
Copyright © 2004–2013, Texas Instruments Incorporated
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