TLE9263QX datasheet(104/164 Pages) INFINEON

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Data Sheet

104

Rev. 1.1, 2014-09-26

TLE9263QX

Supervision Functions

15.2.4

Watchdog during SBC Stop Mode

The watchdog can be disabled for SBC Stop Mode in SBC Normal Mode. For safety reasons, there is a special

sequence to be followed in order to disable the watchdog as described in Figure 51. Two different SPI bits

(WD_STM_ EN_0, WD_STM_ EN_1) in the registers WK_CTRL_1 and WD_CTRL need to be set.

Figure 51

Watchdog disabling sequence in SBC Stop Mode

If a sequence error occurs, then the bit WD_STM_ EN_1 will be cleared and the sequence has to be started again.

The watchdog can be enabled by triggering the watchdog in SBC Stop Mode or by switching back to SBC Normal

Mode via SPI command. In both cases the watchdog will start with a long open window and the bits

WD_STM_EN_1 and WD_STM_ EN_0 are cleared. After the long open window the watchdog has to be served

as configured in the WD_CTRL register.

Note: The bit WD_STM_ EN_0 will be cleared automatically when the sequence is started and it was 1 before.

15.2.5

Watchdog Start in SBC Stop Mode due to Bus Wake

In SBC Stop Mode the Watchdog can be disabled. In addition a feature is available which will start the watchdog

with any BUS wake (CAN or LIN) during SBC Stop Mode. The feature is enabled by setting the bit WD_EN_

WK_BUS = 1

(= default value after POR). The bit can only be changed in SBC Normal Mode and needs to be programmed

before starting the watchdog disable sequence.

A wake on CAN and LINx will generate an interrupt and the RXD pin for LINx or CAN is pulled to low. By these

signals the microcontroller is informed that the watchdog is startedwith a long open window. After the long open

window the watchdog has to be served as configured in the WD_CTRL register.

To disable the watchdog again, the SBC needs to be switched to Normal Mode and the sequence needs to be

sent again.

Correct WD disabling

sequence

Set bit

WD_STM_EN_1 = 1

Set bit

WD_STM_EN_0 = 1

with next WD Trigger

WD is switched off

Sequence Errors

• Missing to set bit

WD_STM_EN_0 with the

next watchdog trigger after

having set WD_STM_EN_1

• Staying in Normal Mode

instead of going to Stop

Mode with the next trigger

Change to

SBC Stop Mode

Before subsequent WD Trigger

Will enable the WD :

• Switching back to SBC

Normal Mode

• Triggering the watchdog

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