ML6411

5

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SWITCHING CHARACTERISTICS

FCLK

Clock input max frequency

30

MHz

Clock input min high time

See Figure 2

15

ns

Clock input min low time

See Figure 2

15

ns

Clamp Gate Width

1.5

µs

Clamp Gate Width

3.5

µs

ANALOG SIGNAL PROCESSING

Y/C Gain Match

CGAIN1 = CGAIN2 = 0

1.01

V/V

Chroma Crosstalk

–60

dB

Differential Gain

2

%

FCLK = 27 MHz

Differential Phase

1

degree

FCLK = 27 MHz

Signal to Noise Ratio

48

dB

FCLK = 20MHz

45

dB

FCLK = 30MHz

Distortion

0.3

%

SFDR

54

dB

TRANSFER FUNCTION

DC integral linearity

@ 27MHz

±0.8

LSB

DC differential linearity

@ 27MHz

±0.5

LSB

GAIN CONTROL

Gain accuracy of UGC for a given gain level

-30mV

30mV

%

Absolute gain error

5%

Gain accuracy for standard preset gain,

1

%

OUTPUT TIMING

Sampling delay

See Figure 2

8

ns

Output hold time

See Figure 2

10

ns

Output delay time

See Figure 2

12

ns

Output enable time

See Figure 2

5

ns

Output disable time

See Figure 2

5

ns

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.