ML6697

4

PIN

NAME

DESCRIPTION

1

(56)

TXCLKIN

Transmit clock TTL input. This 25MHz clock is the frequency reference for the

internal transmit PLL clock multiplier. This pin should be driven by an external

25MHz clock at TTL or CMOS levels.

2

(58, 57)

AGND1

Analog ground.

3, 4

(59,60,

TXD<3:0>

Transmit data TTL inputs. TXD<3:0> inputs accept TX data from the MII. Data

5, 6

61,62)

appearing at TXD<3:0> are clocked into the ML6697 on the rising edge of TXCLK.

7

(63)

TXEN

Transmit enable TTL input. Driving this input high indicates to the ML6697 that

transmit data are present at TXD<3:0>. TXEN edges should be synchronous with

TXCLK.

8

(64)

TXER

Transmit error TTL input. Driving this pin high with TXEN also high causes the part

to continuously transmit scrambled H symbols. When TXEN is low, TXER has no

effect.

9

(1)

TXCLK

Transmit clock TTL output. This 25MHz clock is phase-aligned with the internal

125MHz TX bit clock. Data appearing at TXD<3:0> are clocked into the ML6697 on

the rising edge of this clock.

10, 12, (2, 5,

RXD<3:0>

Receive data TTL outputs. RXD<3:0> outputs are valid on RXCLK’s rising edge.

14, 16 8, 11)

11

(3, 4)

DGND1

Digital ground.

13

(6, 7)

DVCC1

Digital +5V power supply.

15

(9, 10)

DGND2

Digital ground.

17

(12)

RXCLK

Recovered receive clock TTL output. This 25MHz clock is phase-aligned with the

internal 125MHz bit clock recovered from the signal received at TPINP/N. Receive

data at RXD<3:0> changes on the falling edges and should be sampled on the rising

edges of this clock. RXCLK is phase aligned to TXCLKIN when the 100BASE-TX

signal is not present at TPINP/N.

18

(13)

CRS

Carrier Sense TTL output. CRS goes high in the presence of non-idle signals at TPINP/

N. CRS goes low when receive is idle.

19

(14)

RXEN

Receive enable TTL input. When this input is high, all the MII TTL outputs are

enabled. When this input is low, all the MII TTL outputs are in high impedance

mode. This input does not affect MDIO, TXCLK and CRS.

20

(15, 16)

DGND3

Digital ground.

21

(17)

RXDV

Receive data valid TTL output. This output goes high when the ML6697 is receiving

a data packet. RXDV should be sampled synchronously with RXCLK’s rising edge.

22

(18)

DVCC2

Digital +5V power supply.

23

(19)

RXER

Receive error TTL output. This output goes high to indicate error or invalid symbols

within a packet, or corrupted idle between packets. RXER should be sampled

synchronously with RXCLK’s rising edge.

24

(20)

MDC

MII Management Interface clock TTL input. A clock at this pin clocks serial data into

or out of the ML6697’s MII management registers through the MDIO pin. The

maximum clock frequency at MDC is 2.5MHz.