ML6697

8

AC ELECTRICAL CHARACTERISTICS

Over full range of operating conditions unless otherwise specified (Note 1).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

TRANSMITTER (Note 3)

TPOUTP-TPOUTN Differential

Notes 5, 6; for any legal

3.0

5.0

ns

Rise/Fall Time

code sequence

TPOUTP-TPOUTN Differential

Notes 5, 6; for any legal

–0.5

0.5

ns

Rise/Fall Time Mismatch

code sequence

TPOUTP-TPOUTN Differential

Notes 4, 6

–0.5

0.5

ns

Output Duty Cycle Distortion

TPOUTP-TPOUTN Differential

Note 6

300

1400

ps

Output Peak-to-Peak Jitter

TPOUTP-TPOUTN Differential

Notes 6, 7

5

%

Output Voltage Overshoot

TXCLKIN – TXCLK Delay

6

8

11

ns

Transmit Bit Delay

Note 8

10.5

bit times

RECEIVER

Receive Bit Delay (CRS)

Note 9

15.5

bit times

Receive Bit Delay (RXDV)

Note 10

25.5

bit times

MII (Media-Independent Interface)

TX Output Clock Frequency

25MHz frequency

–100

+100

ppm

Tolerance

TXCLKIN pulse width HIGH

14

ns

TXCLKIN pulse width LOW

14

ns

RXCLK pulse width HIGH

14

18

ns

RXCLK pulse width LOW

14

22

ns

Setup time, TXD<3:0> Data

15

ns

Valid to TXCLK Rising Edge

(1.4V point)

Hold Time, TXD<3:0> Data

0

ns

Valid After TXCLK Rising Edge

(1.4V point)

Time that RXD<3:0> Data are

10

20

ns

Valid Before RXCLK Rising Edge

(1.4V point)

Time that RXD<3:0> Data are

10

19

ns

Valid After RXCLK Rising Edge

(1.4V point)

RXCLK 10% – 90% Rise Time

6

ns

RXCLK 90%-10% Fall Time

6ns

RXEN high to RXD<3:0>,

2

10

ns

RXDV, RXER, RXCLK Driving

RXEN low to RXD<3:0>,

2

10

ns

RXDV, RXER, RXCLK

High Impedence