ML6697

5

PIN

NAME

DESCRIPTION

25

(21)

MDIO

MII Management Interface data TTL input/output. Serial data are written to and read

from the ML6697’s management registers through this I/O pin. Input data is sampled

on the rising edge of MDC. Data output should be sampled synchronously with

MDC's rising edge.

26

(22, 23)

DGND4

Digital ground.

27

(24, 25)

DVCC5

Digital +5V power supply.

28

(26, 27)

DGND5

Digital ground.

29

(28)

PHYAD0

MII Serial Management Interface address bit 0.

30

(29)

PHYAD1

MII Serial Management Interface address bit 1.

31

(30)

PHYAD2

MII Serial Management Interface address bit 2.

32

(31)

PHYAD3

MII Serial Management Interface address bit 3.

33

(32)

PHYAD4

MII Serial Management Interface address bit 4.

34

(33)

AVCC3A

Analog +5V power supply.

35

(34)

AVCC3B

Analog +5V power supply.

36

(35)

RGMSET

Equalizer bias resistor input. An external 9.53k

W, 1% resistor connected between

RGMSET and AGND3 sets internal time constants controlling the receive equalizer

transfer function.

37

(36)

RTSET

Transmit level bias resistor input. An external 2.49k

W, 1% resistor connected between

RTSET and AGND3 sets a precision constant bias current for the twisted pair transmit

level.

38

(37, 38)

AGND3

Analog ground.

39, 40 (39, 40)

TPOUTN/P

Transmit twisted pair outputs. This differential current output pair drives MLT-3

waveforms into the network coupling transformer.

41

(41, 42)

AGND2

Analog ground.

42

(43)

AVCC2

Analog +5V power supply.

43

(44)

LINK100

100BASE-TX link activity open-drain output. LINK100 pulls low when there is

100BASE-TX activity at TPINP/N in 100BASE-TX or auto-negotiation modes. This

output is capable of driving an LED directly.

44, 45 (45, 46)

TPINN/P

Receive twisted pair inputs. This differential input pair receives 100BASE-TX signals

from the network.

46

(47)

CMREF

Receiver common-mode reference output. This pin provides a common-mode bias

52

(55)

AVCC1

Analog +5V power supply.