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ML6697 Datasheet(PDF) 1 Page - Micro Linear Corporation |
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ML6697 Datasheet(HTML) 1 Page - Micro Linear Corporation |
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1 / 16 page  1 July 1997 PRELIMINARY ML6697 100BASE-TX Physical Layer with MII GENERAL DESCRIPTION The ML6697 implements the complete physical layer of the Fast Ethernet 100BASE-TX standard. The ML6697 offers a single-chip per-port solution for MII-based repeater applications. The ML6697 interfaces to the controller through the Media Independent Interface (MII). The ML6697 functionality includes 4B/5B encoding/ decoding, Stream Cipher scrambling/descrambling, 125MHz clock recovery/generation, receive adaptive equalization, baseline wander correction, and MLT-3 transmitter. FEATURES n Single-chip 100BASE-TX physical layer n Compliant to IEEE 802.3u 100BASE-TX standard n Supports MII-based repeater applications n Compliant MII (Media Indendent Interface) n 4B/5B encoder/decoder n Stream Cipher scrambler/descrambler n 125MHz clock recovery/generation n Baseline wander correction n Adaptive equalization and MLT-3 encoding/decoding BLOCK DIAGRAM (PLCC Package) 1 TXCLKIN 9 TXCLK 3 TXD3 4 TXD2 5 TXD1 6 TXD0 7 TXEN 8 TXER 40 39 TPOUTP TPOUTN PCS TRANSMIT STATE MACHINE NRZ TO NRZI ENCODER SERIALIZER MLT-3 ENCODER EQUALIZER BLW CORRECTION MLT-3 DECODER LOOPBACK MUX CLOCK AND DATA RECOVERY NRZI TO NRZ DECODER DESERIALIZER FLP/100BASE-TX TWISTED PAIR DRIVER MII MANAGEMENT REGISTERS AND CONTROL LOGIC 37 RTSET 45 TPINP 44 TPINN 46 36 RGMSET 43 CMREF LINK100 18 CRS 19 RXEN 17 RXCLK 10 RXD3 12 RXD2 14 RXD1 16 RXD0 21 RXDV 23 RXER 25 24 30 29 32 31 33 CLOCK SYNTHESIZER PCS RECEIVE STATE MACHINE 5B/4B DECODER DESCRAMBLER 4B/5B ENCODER SCRAMBLER |
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