LMZ14203H

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SNVS692G – JANUARY 2011 – REVISED OCTOBER 2015

Typical Application (continued)

7. Determine module dissipation.

8. Lay out PCB for required thermal performance.

8.2.2.1.1

The enable input provides a precise 1.18-V reference threshold to allow direct logic drive or connection to a

hysteresis resulting in a falling threshold of 1.09 V. The maximum recommended voltage into the EN pin is 6.5 V.

For applications where the midpoint of the enable divider exceeds 6.5 V, a small Zener diode can be added to

limit this voltage.

circuit will be disabled. This implements the feature of programmable under voltage lockout. This is often used in

battery-powered systems to prevent deep discharge of the system battery. It is also useful in system designs for

sequencing of output rails or to prevent early turnon of the supply as the main input voltage rail rises at power

up. Applying the enable divider to the main input rail is often done in the case of higher input voltage systems

such as 24-V AC/DC systems where a lower boundary of operation should be established. In the case of

sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the

LMZ14203H output rail. The two resistors should be chosen based on the following ratio:

(1)

The EN pin is internally pulled up to VIN and can be left floating for always-on operation. However, it is good

will ensure smooth start-up and will prevent overloading the input supply.

8.2.2.1.2

Output Voltage Selection

the divider is connected to the FB input. The voltage at FB is compared to a 0.8-V internal reference. In normal

operation an ON-time cycle is initiated when the voltage on the FB pin falls below 0.8 V. The high-side MOSFET

ON-time cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8 V. As long as the

voltage at FB is above 0.8 V, ON-time cycles will not occur.

(2)

Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:

(3)

These resistors should be chosen from values in the range of 1 k

Ω to 50 kΩ.

usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for

best transient response and minimum output ripple.

8.2.2.1.3

Programmable soft-start permits the regulator to slowly ramp to its steady-state operating point after being

enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to

prevent overshoot.

Upon turnon, after all UVLO conditions have been passed, an internal 8-uA current source begins charging the

external soft-start capacitor. The soft-start time duration to reach steady-state operation is given by the formula:

(4)

Equation 4 can be rearranged as follows:

(5)

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