LMZ14203H datasheet(18/31 Pages) TI

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LMZ14203H

SNVS692G – JANUARY 2011 – REVISED OCTOBER 2015

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Typical Application (continued)

Use of a 4700-pF capacitor results in 0.5-ms soft-start duration. This is a recommended value. Note high values

of CSS capacitance will cause more output voltage droop when a load transient goes across the DCM-CCM

boundary. Use Equation 22 to find the DCM-CCM boundary load current for the specific operating condition. If a

fast load transient response is desired for steps between DCM and CCM mode the soft-start capacitor value

should be less than 0.018 µF.

Note the following conditions will reset the soft-start capacitor by discharging the SS input to ground with an

internal 200-

μA current sink:

•

The enable input being pulled low

•

Thermal shutdown condition

•

Overcurrent fault

•

Internal VINUVLO

8.2.2.1.4

Output Capacitor, CO, Selection

None of the required output capacitance is contained within the module. At a minimum, the output capacitor must

meet the worst-case RMS current rating of 0.5 × ILR P-P, as calculated in Equation 23. Beyond that, additional

capacitance will reduce output ripple so long as the ESR is low enough to permit it. A minimum value of 10

μF is

generally required. Experimentation will be required if attempting to operate with a minimum value. Low-ESR

capacitors, such as ceramic and polymer electrolytic capacitors are recommended.

8.2.2.1.4.1

Capacitance

Equation 6 provides a good first pass approximation of CO for load transient requirements:

CO≥ ISTEP × VFB × L × VIN/ (4 × VO × (VIN — VO) × VOUT-TRAN)

(6)

As an example, for 3-A load step, VIN = 24 V, VOUT = 12 V, VOUT-TRAN = 50 mV:

CO≥ 3 A × 0.8 V × 10 μH × 24 V / (4 x 12V ( 24 V – 12 V) × 50 mV)

(7)

CO≥ 20μF

(8)

8.2.2.1.4.2

ESR

The ESR of the output capacitor affects the output voltage ripple. High ESR will result in larger VOUT peak-to-

peak ripple voltage. Furthermore, high output voltage ripple caused by excessive ESR can trigger the

overvoltage protection monitored at the FB pin. The ESR should be chosen to satisfy the maximum desired VOUT

peak-to-peak ripple voltage and to avoid overvoltage protection during normal operation. The following equations

can be used:

ESRMAX-RIPPLE ≤ VOUT-RIPPLE / ILR P-P

where

•

ILR P-P is calculated using Equation 23.

(9)

ESRMAX-OVP < (VFB-OVP - VFB) / (ILR P-P × AFB )

where

•

AFB is the gain of the feedback network from VOUT to VFB at the switching frequency.

(10)

As worst-case, assume the gain of AFB with the CFF capacitor at the switching frequency is 1.

The selected capacitor should have sufficient voltage and RMS current rating. The RMS current through the

output capacitor is:

I(COUT(RMS)) = ILR P-P / √12

(11)

8.2.2.1.5

Input Capacitor, CIN, Selection

The LMZ14203H module contains an internal 0.47-µF input ceramic capacitor. Additional input capacitance is

required external to the module to handle the input ripple current of the application. This input capacitance should

be as close as possible to the module. Input capacitor selection is generally directed to satisfy the input ripple

current requirements rather than by capacitance value.

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