LM5035

50

0.1 2F

VIN

LM5035

SNVS428H – JANUARY 2006 – REVISED OCTOBER 2015

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8.2.1 Design Requirements

Table 1 lists example design parameters for the application circuit layout in Figure 15.

Table 1. Design Parameters

PARAMETER

MIN

NOM

MAX

UNIT

Input voltage (VIN)

36

72

V

3.3

V

0

30

A

Switching frequency

400

kHz

Efficiency (full load)

89%

Efficiency (half load)

92%

Load regulation

0.2%

Line regulation

0.1%

undervoltage lock-out (ON)

33.9

V

undervoltage lock-out (OFF)

31.9

V

Line overvoltage protection (ON)

79.4

V

Line overvoltage protection (OFF)

78.3

V

8.2.2 Detailed Design Procedure

8.2.2.1 VIN

The voltage applied to the VIN pin, which may be the same as the system voltage applied to the power

the gate charge provided to the output drivers, the switching frequency, and any external loads on the VCC and

REF pins. It is recommended the filter shown in Figure 16 be used to suppress transients which may occur at the

input supply. This is particularly important when VIN is operated close to the maximum operating rating of the

LM5035.

When power is applied to VIN and the UVLO pin voltage is greater than 0.4 V, the VCC regulator is enabled and

supplies current into an external capacitor connected to the VCC pin. When the voltage on the VCC pin reaches

the regulation point of 7.6 V, the voltage reference (REF) is enabled. The reference regulation set point is 5 V.

The HO, LO, SR1, and SR2 outputs are enabled when the two bias regulators reach their set point and the

UVLO pin potential is greater than 1.25 V. In typical applications, an auxiliary transformer winding is connected

through a diode to the VCC pin. This winding must raise the VCC voltage above 8.3 V to shut off the internal

start-up regulator.

After the outputs are enabled and the external VCC supply voltage has begun supplying power to the IC, the

current into VIN drops below 1 mA. VIN must remain at a voltage equal to or above the VCC voltage to avoid

reverse current through protection diodes.

Figure 16. Input-Transient Protection

22

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