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HDV24VL Datasheet(PDF) 14 Page - AMIC Technology

Part # HDV24VL
Description  2.8 Volt x16 Very Low Power Dual-Port Static RAM
PDF  18 Pages
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Manufacturer  AMICC [AMIC Technology]
Direct Link  http://www.amictechnology.com
Logo AMICC - AMIC Technology

HDV24VL Datasheet(HTML) 14 Page - AMIC Technology

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© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
HDV24VL
October 2003
ADP II
3HD166B
Page 14 of 14
ADDRA
t WC
Match
t WP
t DW
Valid
t DH
t APS
tBAA
t DDD
tBDA
t BDD
BUSYB
R/WA
DATA INA
ADDRB
DATA OUTB
Valid
t WDD
NOTES:
1. tAPS is ignored fo r SLAVE part (M/ S
___
= VIL)
2. CE
_____
L
=CE
_____
R
= VIH.
3. OE
_____
= VIL for the reading port.
4. For SLAVE mode (M/ S
___
= VIL), BUSY
___________
is an input.
5. Timing for both ports is the same. Port B is opposite of port A.
Diagram 7. Write with Port-to-Port Read and BUSY
___________
(M/S
__
= VIH)
R/WA
BUSYB
R/WB
t WB
t WP
tWH
NOTES:
1. SLAVE (BUSY
___________
input) and MASTER (BUSY
___________
output) must meet t WH.
2. BUSY
___________
is sent to port B blocking R/ W
____
B
till BUSY
___________
B
=VIH.
3. tWB is for SLAVE mode.
Diagram 8. Write with BUSY
___________
(M/S
__
= VIL)
ADDRA
and
ADDRB
AddressesMatch
CE A
CE B
BUSYB
tAPS
tBAC
tBDC
Diagram 9. BUSY
___________
Arbitration Controlled by CE
_____
Timing (M/S
__
= VIH)



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