SM5050A

NIPPON PRECISION CIRCUITS—2

BLOCK DIAGRAM

PIN DESCRIPTION

SM5050AV

CF5050A

1. Ip = input with built-in pull-up resistor.

Description

Number

Name

Name

P ad dimensions [µm]

XY

1

P 1

P 1

620

1330

Ip

Program input 1. Selects the output frequency multiplier ratio.

2

VSS

V S S

290

1132

–

Ground

VSSQ

2 9 0

9 2 0

–

Output circuit ground

3

Q

Q

2 9 0

5 6 9

O

Output (CMOS)

4

VDD

VDDQ

5 4 0

2 4 0

–

Output circuit supply

V D D

9 0 6

2 4 0

–

Supply

5

X T N

X T N

1524

240

O

Cr ystal oscillator connection pins.

Cr ystal connected between XT and XTN.

6

X T

X T

1870

542

I

7

INHN

INHN

1870

1015

Ip

O p e rating state control (inhibit).

When INHN is LOW , output is high impedance and PLL circuits stop.

8

P 0

P 0

1540

1330

Ip

Program input 0. Selects the output frequency multiplier ratio.

VCO

XT

XTN

LPF

Q

P0

P1

INHN

Phase

Detector

Charge

Pump

Oscillator

R-counter

Duty

Control

Circuit

Output

Buffer

N-counter

Control

Circuit

VDDQ

VDD

VSSQ

VSS