MT8930CE datasheet(17/42 Pages) MITEL

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MT8930C

9-49

set HIGH, before writing the next byte into the FIFO.

This bit is cleared automatically once the byte is

written to the Transmit FIFO.

When the ‘ﬂagged’

byte reaches the bottom of the FIFO, a frame abort

sequence is sent instead of the byte and the

transmitter operation returns to normal. The frame

abort sequence is ignored if the packet has less then

two bytes.

iii) Transparent Data Transfer

The Trans bit (B4) in the HDLC Control Register 2

can be set to provide transparent data transfer by

disabling the protocol functions. The transmitter no

longer generates the Flag, Abort and Idle sequences

nor does it insert the zeros and calculate the FCS.

It should be noted that none of the protocol related

status or interrupt bits are applicable in transparent

data transfer state. However, the FIFO related status

and interrupt bits are pertinent and carry the same

meaning as they do while performing the protocol

functions.

HDLC Receiver

After a reset on power up, the receive section is

disabled. Address detection is also disabled when a

reset occurs.

If address detection is required, the

Receiver Address Registers are loaded with the

desired address and the ADRec bit in the HDLC

Control Register 1 is set HIGH. The receive section

can then be enabled by RxEN bit in this same

Control Register 1. All HDLC interrupts are masked,

thus the desired interrupt signal must be unmasked

through the HDLC Interrupt Mask Register. All active

interrupts are cleared by reading the HDLC Interrupt

Status Register.

i) Normal Packets

After initialization as explained above, the serial data

starts to be clocked in and the receiver checks for

the idle channel and ﬂags.

If an idle channel is

detected, the ‘Idle’ bit in the HDLC Status Register is

set HIGH.

Once a ﬂag is detected, the receiver

synchronizes itself in a bytewide manner to the

incoming

data

stream.

The

receiver

keeps

resynchronizing to the ﬂags until an incoming packet

appears.

The incoming packet is examined on a

bit-by-bit basis, inserted zeros are deleted, the FCS

is calculated and the data bytes are written into the

19 byte Receive FIFO. However, the FCS and other

control characters, i.e., ﬂag and abort , are never

stored in the Receive FIFO. If the address detection

is enabled, the address ﬁeld following the ﬂag is

compared to the bytes in the Receive Address

Registers.

If one byte address recognition is

enabled, the address ﬁeld is one byte long and it is

compared with the six most signiﬁcant bits in

address recognition register 1. If two byte address

recognition is enabled, the address ﬁeld is two bytes

long and is compared with the address recognition

registers 1 and 2.

The address byte can also be

recognized if it is an all call address (i.e., seven most

signiﬁcant bits are 1). If a match is not found, the

entire packet is ignored, nothing is written to the

Receive FIFO and the receiver waits for the next

packet. If the active address byte is valid, the packet

is received in normal fashion.

All the bytes written to the receive FIFO are ﬂagged

with two status bits. The status bits are found in the

HDLC status register and indicate whether the byte

to be read from the FIFO is the ﬁrst byte of the

packet, the middle of the packet, the last byte of the

packet with good FCS or the last byte of the packet

with bad FCS. This status indication is valid for the

byte which is to be read from the Receive FIFO.

The incoming data is always written to the FIFO in a

bytewide manner. However, in the event of data sent

not being a multiple of eight bits, the software

associated with the receiver should be able to pick

the data bits from the LSB positions of the last byte

in the received data written to the FIFO.

The

Protocoller does not provide any indication as to how

many bits this might be.

ii) Invalid Packets

In TE mode, if there are less than 25 data bits

between the opening and closing ﬂags, the packet is

considered invalid and the data never enters the

receive FIFO (inserted zeros do not form part of the

valid bit count). This is true even with data and the

abort sequence, the total of which is less than 25

bits. The data packets that are at least 25 bits but

less than 32 bits long are also invalid, but not

ignored. They are clocked into the receive FIFO and

tagged as having bad FCS.

In NT mode, however, all the data packets that are

less than 32 bits long are considered invalid. They

are clocked into the receive FIFO with “Bad FCS”

status.

iii) Frame Abort

When a frame abort is received, the EOPD and FA

bits in the HDLC Interrupt Status Register are set.

The last byte of the aborted packet is written to the

FIFO with a status of “Packet Byte”. If there is more

than one packet in the FIFO, the aborted packet is

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