MT8930CE datasheet(4/42 Pages) MITEL

4 / 42 page

MT8930C

9-36

SYNC/BA Synchronization/Bus Activity Output (Cmode = 0): output indicating synchronization

to incoming RX frames when activation request is asserted and the deactivation request

is ’0’ (AR = 1 and DR = 0). Synchronization is declared once three successive frames

conforming to the 14-bit bipolar violation criteria have been detected. If part is

deactivated or activation request is ’0’ (AR = 0 or DR = 1), this pin indicates the

presence of bus activity.

MFR

Multiframe Input/Output (Cmode=0): multiframe input in NT mode or output in TE

mode. Setting this pin to one in NT mode when HALF = 1, forces the FA, N pair to 1, 0

respectively. This pin going high in TE mode indicates that FA= 1 & N= 0 has been

received. This signal is updated on the rising edge of the HALF signal.

MCH

Maintenance Channel (Q-channel) Input/Output (Cmode=0): an output in NT mode

which is valid only in the frame following the transmission of MFR. In TE mode, this is

the maintenance channel (Q-channel) input which is transmitted in the FA and L bits

following the reception of the multiframe signal. This input is sampled on the falling

edge of the HALF signal.

M/S

M/S Input/Output (Cmode=0): M/S bit input in NT mode or M/S bit output in TE mode.

M is read or written when HALF=1 while S is read or written when HALF=0.

Activate Request Input (Cmode = 0): asserting AR with DR = 0 will initiate the

appropriate S-interface activation sequence coded in the NT or TE activation/

deactivation controller.

Deactivate Request Input (Cmode = 0): asserting DR high will initiate the appropriate

S-interface deactivation sequence coded in the NT or TE activation/ deactivation

controller.

Rsti

Reset Input: Schmitt trigger reset input. If ’0’, sets all control registers to the default

conditions, resets activation state machines to the deactivated state, resets HDLC,

clears the HDLC FIFO‘s. Sets the microport to Motorola bus mode.

STAR/Rsto Star/Reset (Open Drain Output): 192kbit/s Rx data output ﬁxed relative to the ST-

BUS timebase. A group of NTs, in ﬁxed timing mode, can be wire or’ed together to

create a Star conﬁguration. Active low reset output in TE mode indicating 128

consecutive marks have been received. Can be connected directly to Rsti to allow NT

to reset all TEs on the bus. This pin must be tied to VDD with a 10 kΩ resistor.

LRx

Receive Line Signal Input: this is a high impedance input for the pseudoternary line

signal to be connected to the line through a 2:1 ratio transformer. See Figures 20 and

21. A DC bias level on this input equal to VBias must be maintained.

LTx

Transmit Line Signal Output: this is a current source output designed to drive a

nominal 50 ohm line through a 2:1 ratio transformer. See Figures 20 and 21.

VBias

Bias Voltage: analog ground for Tx and Rx transformers. This pin must be decoupled

to V

through a 10

µF capacitor with good high frequency characteristics (i.e.,

tantalum).

VDD

Power Supply Input.

1,5-6,10-

12,15,18,

23,27-

29, 33,

36, 39, 41

No Connection.

Pin Description (continued)

Pin #

Name

Description

DIP

PLCC

MT8930CE Datasheet(PDF) 4 Page - Mitel Networks Corporation

MT8930CE Datasheet(HTML) 4 Page - Mitel Networks Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL